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[/] [uart16550/] [trunk/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5567d 21h /uart16550/trunk/
105 Timeout interrupt should be generated only when there is at least ony
character in the fifo.		 igorm 7136d 22h /trunk/
103 Brandl Tobias repaired a bug regarding frame error in receiver when brake is received. tadejm 7293d 16h /trunk/
101 Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. tadejm 7321d 18h /trunk/
100 Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs. tadejm 7321d 19h /trunk/
99 Added synchronizer flops for RX input. tadejm 7321d 19h /trunk/
98 Added to synchronize RX input to Wishbone clock. tadejm 7321d 19h /trunk/
96 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish. tadejm 7377d 03h /trunk/
95 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish. tadejm 7377d 03h /trunk/
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7377d 03h /trunk/
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7377d 03h /trunk/
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7490d 20h /trunk/
91 Removed files due to new complete testbench. tadejm 7491d 11h /trunk/
90 Add Flextronics header avisha 7493d 18h /trunk/
89 adjusted comment + define dries 7574d 00h /trunk/
88 added clearing the receiver fifo statuses on resets gorban 7636d 13h /trunk/
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7666d 14h /trunk/
86 restored include for uart_defines.v in uart_test.v gorban 7936d 18h /trunk/
85 Updated documentation to include latest changes. gorban 7970d 10h /trunk/
84 The uart_defines.v file is included again in sources. gorban 7983d 10h /trunk/
83 Reverted to include uart_defines.v file in other files again. gorban 7983d 10h /trunk/
82 Updated to work with latest core. gorban 7990d 08h /trunk/
81 Added lastest additions. gorban 7990d 08h /trunk/
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7990d 08h /trunk/
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7990d 08h /trunk/
75 Endian define added. Big Byte Endian is selected by default. mohor 8143d 14h /trunk/
74 tf_overrun signal was disabled since it was not used gorban 8148d 15h /trunk/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8155d 15h /trunk/
72 UART PHY added. Files are fully operational, working on HW. mohor 8168d 22h /trunk/
71 Removed confusing comment gorban 8180d 11h /trunk/

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