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Rev 3 → Rev 4

/fht_mtx_tm_8x8.v File deleted
/fht_bfly.v
1,12 → 1,24
//
// File: fht_8x8_core.v
// Author: Ivan Rezki
// Topic: RTL Core
// 2-Dimensional Fast Hartley Transform
//
/**********************************************************************
* File : fht_8x8_core.v
* Author: Ivan Rezki
* email : irezki@gmail.com
* Topic : RTL Core
* 2-Dimensional Fast Hartley Transform
*
* Function: Fast Hartley Transform ButterFly Unit
*
* RIGHT TO USE: This code example, or any portion thereof, may be
* used and distributed without restriction, provided that this entire
* comment block is included with the example.
*
* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
* USE OF THIS CODE.
**********************************************************************/
 
// Fast Hartley Transform ButterFly Unit
 
module fht_bfly(
rstn,
clk,
/mtx_trps_8x8_dpsram.v
1,18 → 1,30
//
// File: mtx_trps_8x8_dpsram.v
// Author: Ivan Rezki
// Topic: RTL Core
// 2-Dimensional Fast Hartley Transform
//
/**********************************************************************
* File : mtx_trps_8x8_dpsram.v
* Author: Ivan Rezki
* email : irezki@gmail.com
* Topic : RTL Core
* 2-Dimensional Fast Hartley Transform
*
*
* Matrix Transpose 8x8
* DPSRAM-based Double Buffer
* Buffer size is 64*2 words, each word is 16 bits
*
* Matrix Transpose -> 64 clk delay
* - Double Buffer Solution:
*
* RIGHT TO USE: This code example, or any portion thereof, may be
* used and distributed without restriction, provided that this entire
* comment block is included with the example.
*
* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
* USE OF THIS CODE.
**********************************************************************/
 
// Matrix Transpose 8x8
// DPSRAM-based Double Buffer
// Buffer size is 64*2 words, each word is 16 bits
 
// Matrix Transpose -> 64 clk delay
// - Double Buffer Solution:
 
 
module mtx_trps_8x8_dpsram (
rstn,
sclk,
53,25 → 65,36
wire wr_CSN;
wire wr_WEN;
 
wire [15:0] rd_DATA;
wire [ 6:0] rd_ADDR;
wire rd_CSN;
 
dpsram_128x16 u_dpsram(
.addra (wr_ADDR),
.addrb (rd_ADDR),
.clka (sclk),
.clkb (sclk),
.dina (wr_DATA),
.dinb ({16{1'b0}}),
.douta (/* OPEN */),
.doutb (rd_DATA),
.ena (wr_CSN),
.enb (rd_CSN),
.wea (wr_WEN),
.web (1'b1)
);
`ifdef USE_FPGA_SPSRAM
wire [15:0] rd_DATA;
dpsram_128x16 u_dpsram(
.addra (wr_ADDR),
.addrb (rd_ADDR),
.clka (sclk),
.clkb (sclk),
.dina (wr_DATA),
.dinb ({16{1'b0}}),
.douta (/* OPEN */),
.doutb (rd_DATA),
.ena (wr_CSN),
.enb (rd_CSN),
.wea (wr_WEN),
.web (1'b1)
);
`endif
 
`ifdef USE_ASIC_SPSRAM
reg [15:0] rd_DATA = 16'd0;
reg [15:0] sram[0:127];
always @(posedge sclk)
if (~wr_WEN && ~wr_CSN) sram[wr_ADDR] <= wr_DATA; // Write
always @(posedge sclk)
if ( 1'b1 && ~rd_CSN) rd_DATA <= sram[rd_ADDR]; // Read
`endif
 
always @(posedge sclk or negedge rstn)
if (!rstn) cnt128d_wr <= #1 0;
else if (inp_valid) cnt128d_wr <= #1 cnt128d_wr + 1;
115,7 → 138,7
 
// synopsys translate_off
// <<<------------- DUMP Section
 
/*
// 2D FHT OUTPUT DUMP DATA
parameter MEM_TRPS_DPSRAM_FILE = "./result/mem_trps_dpsram.txt";
integer mem_trps_dpsram_dump;
123,6 → 146,6
 
always @(posedge sclk)
if (mem_valid) $fdisplay(mem_trps_dpsram_dump,"%h",mem_data);
 
*/
// synopsys translate_on
endmodule
/signed_mult_const_fpga.v
1,27 → 1,40
//
// File: signed_mult_const_fpga.v
// Author: Ivan Rezki
// Topic: RTL Core
// 2-Dimensional Fast Hartley Transform
//
/**********************************************************************
* File : signed_mult_const_fpga.v
* Author: Ivan Rezki
* email : irezki@gmail.com
* Topic : RTL Core
* 2-Dimensional Fast Hartley Transform
*
*
* Function: Signed Multiplier - constant sqrt(2) = 1.41421
*
* 8 bit accuracy:
* 1.41421*a = (256*1.41421)*a/256 = 362.03776*a/256 = 362*a/256
* product = 362*a/2^8
* wire [8:0] mult_constant = 9'd362;
*
* 15 bit accuracy:
* 1.41421*a = (32768*1.41421)*a/32768 = 46340.95*a/32768
* product = 46341*a/2^15
* wire [15:0] mult_constant = 16'd46341;
*
* 16 bit accuracy:
* 1.41421*a = (65536*1.41421)*a/65536 = 92681*a/65536
* product = 92681*a/2^16
* wire [16:0] mult_constant = 17'd92681;
*
* RIGHT TO USE: This code example, or any portion thereof, may be
* used and distributed without restriction, provided that this entire
* comment block is included with the example.
*
* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
* USE OF THIS CODE.
**********************************************************************/
 
// Signed Multiplier - constant sqrt(2) = 1.41421
 
// 8 bit accuracy:
// 1.41421*a = (256*1.41421)*a/256 = 362.03776*a/256 = 362*a/256
// product = 362*a/2^8
// wire [8:0] mult_constant = 9'd362;
 
// 15 bit accuracy:
// 1.41421*a = (32768*1.41421)*a/32768 = 46340.95*a/32768
// product = 46341*a/2^15
// wire [15:0] mult_constant = 16'd46341;
 
// 16 bit accuracy:
// 1.41421*a = (65536*1.41421)*a/65536 = 92681*a/65536
// product = 92681*a/2^16
// wire [16:0] mult_constant = 17'd92681;
 
module signed_mult_const_fpga (
rstn,
clk,
/signed_mult_const_asic.v
1,14 → 1,27
//
// File: signed_mult_const_asic.v
// Author: Ivan Rezki
// Topic: RTL Core
// 2-Dimensional Fast Hartley Transform
//
/**********************************************************************
* File : signed_mult_const_asic.v
* Author: Ivan Rezki
* email : irezki@gmail.com
* Topic : RTL Core
* 2-Dimensional Fast Hartley Transform
*
*
* Function: Signed Multiplier - constant sqrt(2) = 1.41421
* 1.41421*a = (256*1.41421)*a/256 = 362.03776*a/256 = 362*a/256
* product = 362*a/2^8
*
* RIGHT TO USE: This code example, or any portion thereof, may be
* used and distributed without restriction, provided that this entire
* comment block is included with the example.
*
* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
* USE OF THIS CODE.
**********************************************************************/
 
// Signed Multiplier - constant sqrt(2) = 1.41421
// 1.41421*a = (256*1.41421)*a/256 = 362.03776*a/256 = 362*a/256
// product = 362*a/2^8
 
module signed_mult_const_asic (
rstn,
clk,
/fht_8x8_core.v
1,51 → 1,78
//
// File: fht_8x8_core.v
// Author: Ivan Rezki
// Topic: RTL Core
// 2-Dimensional Fast Hartley Transform
//
/**********************************************************************
* File : fht_8x8_core.v
* Author: Ivan Rezki
* email : irezki@gmail.com
* Topic : RTL Core
* 2-Dimensional Fast Hartley Transform
*
* Compilation Notes:
* 1).Memory
* - if you use Xilinx FPGA for prototyping
* compile this code along with
* USE_FPGA_SPSRAM definition and
* XilinxCoreLib library,
* - otherwise compile this code
* along with USE_ASIC_SPSRAM
* 2).Multiplier
* - if you use Xilinx FPGA for prototyping
* compile this code along with
* USE_FPGA_MULT definition
* - otherwise compile this code
* along with USE_ASIC_MULT
*
* TOP Level
* 2D FHT 64 points -> ... clk delay
*
* +------------------------+
* | |
* --->| 2D FHT/64 Points |--->
* | |
* +------------------------+
* |<---- .. clk delay ---->|
*
*
* Data is coming from somewhere (e.g. memory) with sclk one by one.
* 1st step 1D FHT by rows:
* - Shift Register for 8 points -> ... clk delay
* - Alligner
* - Calculate 1D FHT for 8 points. -> ... clk delay
* - FF is used on the each input of the butterfly
* - FF is used on the input of the multiplier
* 2nd Step:
* Matrix Transpose -> 64+1 clk delay
* - Collecting data until 1st buffer is full as 64 points.
* - Read 64 points right away after 1st buffer is full.
* - At the same time 2nd buffer is ready to receive data.
* - Collecting data until 2nd buffer is full as 64 points.
* - Read 64 points right away after 2nd buffer is full.
* - At the same time 1st buffer is ready to receive data once again.
* - ...
* 3rd Step 1D FHT by columns.
* - Combine data to make 8 points in parallel. -> ... clk delay
* - Calculate 1D FHT for 8 points. -> ... clk delay
*
* RIGHT TO USE: This code example, or any portion thereof, may be
* used and distributed without restriction, provided that this entire
* comment block is included with the example.
*
* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
* USE OF THIS CODE.
**********************************************************************/
 
// TOP Level
// 2D FHT 64 points -> ... clk delay
//
// +------------------------+
// | |
// --->| 2D FHT/64 Points |--->
// | |
// +------------------------+
// |<---- .. clk delay ---->|
//
 
// Data is coming from somewhere (e.g. memory) with sclk one by one.
// 1st step 1D FHT by rows:
// - Shift Register for 8 points -> ... clk delay
// - Alligner
// - Calculate 1D FHT for 8 points. -> ... clk delay
// - FF is used on the each input of the butterfly
// - FF is used on the input of the multiplier
// 2nd Step:
// Matrix Transpose -> 64+1 clk delay
// - Collecting data until 1st buffer is full as 64 points.
// - Read 64 points right away after 1st buffer is full.
// - At the same time 2nd buffer is ready to receive data.
// - Collecting data until 2nd buffer is full as 64 points.
// - Read 64 points right away after 2nd buffer is full.
// - At the same time 1st buffer is ready to receive data once again.
// - ...
// 3rd Step 1D FHT by columns.
// - Combine data to make 8 points in parallel. -> ... clk delay
// - Calculate 1D FHT for 8 points. -> ... clk delay
 
// NOTES:
// 1. Matrix Transposition maximum data width is 16 bits.
 
// ----->>> Define Multiplier Type
//`define USE_ASIC_MULT
`define USE_ASIC_MULT
//`define USE_FPGA_MULT
 
// ----->>> Define Memory Type
//`define USE_FPGA_SPSRAM
//`define USE_ASIC_SPSRAM
`define USE_ASIC_SPSRAM
 
module fht_8x8_core (
rstn,
91,16 → 118,6
// +++--->>> Matrix Transposition <<<---+++ \\
wire mem_valid;
wire [N+2:0] mem_data;
//mtx_trps_8x8_spsram #(N+3) u2_mtx_ts (
// .rstn (rstn),
// .sclk (sclk),
//
// .inp_valid (fht_1d_valid),
// .inp_data (fht_1d_data),
//
// .mem_mux_data (mem_data),
// .mem_mux_valid (mem_valid)
//);
 
mtx_trps_8x8_dpsram #(N+3) u2_mtx_ts (
.rstn (rstn),
/fht_1d_x8.v
1,21 → 1,31
//
// File: fht_1d_x8.v
// Author: Ivan Rezki
// Topic: RTL Core
// 2-Dimensional Fast Hartley Transform
//
/**********************************************************************
* File : fht_1d_x8.v
* Author: Ivan Rezki
* email : irezki@gmail.com
* Topic : RTL Core
* 2-Dimensional Fast Hartley Transform
*
* Function: Fast Hartley Transform 1 Dimension for 8 Points
* Decimation in Frequency Domain
*
* +-----------+ +-----------+ +-----------+
* | Serial | | 1D FHT | | Parallel |
* --->| to |--->| |--->| to |--->
* | Parallel | | 8 Points | | Serial |
* +-----------+ +-----------+ +-----------+
*
* RIGHT TO USE: This code example, or any portion thereof, may be
* used and distributed without restriction, provided that this entire
* comment block is included with the example.
*
* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
* USE OF THIS CODE.
**********************************************************************/
 
// Fast Hartley Transform 1 Dimension for 8 Points
// Decimation in Frequency Domain
 
//
// +-----------+ +-----------+ +-----------+
// | Serial | | 1D FHT | | Parallel |
// --->| to |--->| |--->| to |--->
// | Parallel | | 8 Points | | Serial |
// +-----------+ +-----------+ +-----------+
//
 
module fht_1d_x8(
rstn,
sclk,
/fht_bfly_noFF.v
1,12 → 1,24
//
// File: fht_8x8_core.v
// Author: Ivan Rezki
// Topic: RTL Core
// 2-Dimensional Fast Hartley Transform
//
/**********************************************************************
* File : fht_8x8_core.v
* Author: Ivan Rezki
* email : irezki@gmail.com
* Topic : RTL Core
* 2-Dimensional Fast Hartley Transform
*
* Function: Fast Hartley Transform ButterFly Unit without input FF
*
* RIGHT TO USE: This code example, or any portion thereof, may be
* used and distributed without restriction, provided that this entire
* comment block is included with the example.
*
* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
* USE OF THIS CODE.
**********************************************************************/
 
// Fast Hartley Transform ButterFly Unit without input FF
 
module fht_bfly_noFF(
a,
b,

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