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Rev Log message Author Age Path
46 x1 mikel262 5311d 10h /
45 stall re-added mikel262 5311d 10h /
44 stall re-added mikel262 5311d 10h /
43 stall readded mikel262 5311d 10h /
42 Added backpressure/stallability of output interface. mikel262 5314d 21h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5452d 09h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5495d 00h /
39 bug fix. mikel262 5497d 22h /
38 Reduced processing latency of Huffman encoding mikel262 5522d 22h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5527d 02h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5528d 22h /
35 Added check for image width in testbench. mikel262 5529d 11h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5529d 19h /
33 mikel262 5530d 04h /
32 mikel262 5530d 23h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5534d 00h /
30 mikel262 5534d 12h /
29 mikel262 5534d 20h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5534d 20h /
27 mikel262 5537d 09h /
26 mikel262 5537d 09h /
25 moved from branch to trunk mikel262 5537d 09h /
24 mikel262 5537d 10h /
23 mikel262 5538d 20h /
22 Changed divider to use reciprocal lookup table. Improved Huffman processing time. BUF_FIFO almost full signal modified. mikel262 5539d 21h /
21 Huffman.vhd processing latency shortened. mikel262 5540d 20h /
20 Added compressed JPEG output file from testbench mikel262 5540d 21h /
19 Timing improved in MDCT and in Huffman mikel262 5540d 23h /
18 Huffman old design restored. Simulation HOWTO added. mikel262 5540d 23h /
17 return to original version, better timing, smaller area but higher processing time mikel262 5541d 19h /

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