URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
96	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish.	tadejm	7381d 08h	/
95	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish.	tadejm	7381d 08h	/
94	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7381d 08h	/
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7381d 08h	/
92	This is revision 1.4, revision 1.5 was put there by mistake.	simons	7495d 01h	/
91	Removed files due to new complete testbench.	tadejm	7495d 16h	/
90	Add Flextronics header	avisha	7497d 23h	/
89	adjusted comment + define	dries	7578d 04h	/
88	added clearing the receiver fifo statuses on resets	gorban	7640d 18h	/
87	This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.	gorban	7670d 19h	/
86	restored include for uart_defines.v in uart_test.v	gorban	7940d 23h	/
85	Updated documentation to include latest changes.	gorban	7974d 15h	/
84	The uart_defines.v file is included again in sources.	gorban	7987d 15h	/
83	Reverted to include uart_defines.v file in other files again.	gorban	7987d 15h	/
82	Updated to work with latest core.	gorban	7994d 13h	/
81	Added lastest additions.	gorban	7994d 13h	/
80	Remove uart_fifo.v because it is replaced by other 2 files.	gorban	7994d 13h	/
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7994d 13h	/
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8147d 19h	/
77	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		8147d 19h	/

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