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Rev Log message Author Age Path
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7381d 13h /
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7381d 13h /
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7495d 06h /
91 Removed files due to new complete testbench. tadejm 7495d 21h /
90 Add Flextronics header avisha 7498d 04h /
89 adjusted comment + define dries 7578d 10h /
88 added clearing the receiver fifo statuses on resets gorban 7640d 23h /
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7671d 01h /
86 restored include for uart_defines.v in uart_test.v gorban 7941d 05h /
85 Updated documentation to include latest changes. gorban 7974d 21h /
84 The uart_defines.v file is included again in sources. gorban 7987d 20h /
83 Reverted to include uart_defines.v file in other files again. gorban 7987d 20h /
82 Updated to work with latest core. gorban 7994d 18h /
81 Added lastest additions. gorban 7994d 18h /
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7994d 18h /
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7994d 18h /
78 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8148d 00h /
77 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 8148d 00h /
76 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 8148d 00h /
75 Endian define added. Big Byte Endian is selected by default. mohor 8148d 00h /

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