URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

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Rev	Log message	Author	Age	Path
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8148d 07h	/
77	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		8148d 07h	/
76	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		8148d 07h	/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8148d 07h	/
74	tf_overrun signal was disabled since it was not used	gorban	8153d 08h	/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8160d 07h	/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8173d 15h	/
71	Removed confusing comment	gorban	8185d 03h	/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8190d 12h	/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8199d 03h	/
68	lsr[7] was not showing overrun errors.	mohor	8202d 10h	/
67	Missing declaration of rf_push_q fixed.	mohor	8209d 10h	/
66	rx push changed to be only one cycle wide.	mohor	8209d 10h	/
65	Warnings fixed (unused signals removed).	mohor	8210d 15h	/
64	Warnings cleared.	mohor	8210d 15h	/
63	Synplicity was having troubles with the comment.	mohor	8210d 16h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8211d 14h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8212d 09h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8212d 13h	/
59	MSR register fixed.	mohor	8215d 10h	/

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Subversion Repositories uart16550

[/] - Rev 78

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