OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_3/] [bench/] - Rev 106

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 New directory structure. root 5572d 08h /uart16550/tags/rel_3/bench/
102 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7326d 06h /uart16550/tags/rel_3/bench/
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7381d 14h /uart16550/tags/rel_3/bench/
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7381d 14h /uart16550/tags/rel_3/bench/
91 Removed files due to new complete testbench. tadejm 7495d 22h /uart16550/tags/rel_3/bench/
86 restored include for uart_defines.v in uart_test.v gorban 7941d 06h /uart16550/tags/rel_3/bench/
83 Reverted to include uart_defines.v file in other files again. gorban 7987d 21h /uart16550/tags/rel_3/bench/
72 UART PHY added. Files are fully operational, working on HW. mohor 8173d 09h /uart16550/tags/rel_3/bench/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8225d 21h /uart16550/tags/rel_3/bench/
38 small update to test interrupts gorban 8252d 00h /uart16550/tags/rel_3/bench/
17 added empty directories for the required structure. gorban 8338d 23h /uart16550/tags/rel_3/bench/
14 gorban 8339d 02h /uart16550/tags/rel_3/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.