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Rev Log message Author Age Path
106 New directory structure. root 5571d 12h /
105 Timeout interrupt should be generated only when there is at least ony
character in the fifo.		 igorm 7140d 13h /
104 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7297d 07h /
103 Brandl Tobias repaired a bug regarding frame error in receiver when brake is received. tadejm 7297d 07h /
102 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7325d 09h /
101 Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. tadejm 7325d 09h /
100 Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs. tadejm 7325d 10h /
99 Added synchronizer flops for RX input. tadejm 7325d 10h /
98 Added to synchronize RX input to Wishbone clock. tadejm 7325d 10h /
97 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7380d 18h /
96 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish. tadejm 7380d 18h /
95 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish. tadejm 7380d 18h /
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7380d 18h /
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7380d 18h /
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7494d 11h /
91 Removed files due to new complete testbench. tadejm 7495d 02h /
90 Add Flextronics header avisha 7497d 09h /
89 adjusted comment + define dries 7577d 14h /
88 added clearing the receiver fifo statuses on resets gorban 7640d 04h /
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7670d 05h /
86 restored include for uart_defines.v in uart_test.v gorban 7940d 09h /
85 Updated documentation to include latest changes. gorban 7974d 01h /
84 The uart_defines.v file is included again in sources. gorban 7987d 01h /
83 Reverted to include uart_defines.v file in other files again. gorban 7987d 01h /
82 Updated to work with latest core. gorban 7993d 23h /
81 Added lastest additions. gorban 7993d 23h /
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7993d 23h /
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7993d 23h /
78 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8147d 05h /
77 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 8147d 05h /

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