| Line 72... |
Line 72... |
signal iram_rdata : std_logic_vector(23 downto 0);
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signal iram_rdata : std_logic_vector(23 downto 0);
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signal iram_wren : std_logic;
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signal iram_wren : std_logic;
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signal iram_rden : std_logic;
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signal iram_rden : std_logic;
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signal sim_done : std_logic;
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signal sim_done : std_logic;
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signal iram_fifo_afull : std_logic;
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signal iram_fifo_afull : std_logic;
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signal outif_almost_full : std_logic;
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signal count1 : unsigned(15 downto 0);
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------------------------------
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------------------------------
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-- architecture begin
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-- architecture begin
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------------------------------
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------------------------------
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begin
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begin
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| Line 148... |
Line 149... |
iram_fifo_afull => iram_fifo_afull,
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iram_fifo_afull => iram_fifo_afull,
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-- OUT RAM
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-- OUT RAM
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ram_byte => ram_byte,
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ram_byte => ram_byte,
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ram_wren => ram_wren,
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ram_wren => ram_wren,
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ram_wraddr => ram_wraddr
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ram_wraddr => ram_wraddr,
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outif_almost_full => outif_almost_full
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);
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);
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- OUT RAM
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-- OUT RAM
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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| Line 201... |
Line 203... |
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wait;
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wait;
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end process;
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end process;
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backpressure : process(CLK, RST)
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begin
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if RST = '1' then
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outif_almost_full <= '0';
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count1 <= (others => '0');
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elsif CLK'event and CLK = '1' then
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if count1 = 10000 then
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count1 <= (others => '0');
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outif_almost_full <= not outif_almost_full;
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else
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count1 <= count1 + 1;
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end if;
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end if;
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end process;
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end TB;
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end TB;
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-----------------------------------
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-----------------------------------
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--**************************************************************************--
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--**************************************************************************--
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