| Line 5... |
Line 5... |
--
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--
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-- Module : ZZ_TOP
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-- Module : ZZ_TOP
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--
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--
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-- Content : ZigZag Top level
|
-- Content : ZigZag Top level
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--
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--
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-- Description : Zig Zag scan and Quantizer
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-- Description : Zig Zag scan
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--
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--
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-- Spec. :
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-- Spec. :
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--
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--
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-- Author : Michal Krepa
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-- Author : Michal Krepa
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--
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--
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| Line 49... |
Line 49... |
-- CTRL
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-- CTRL
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start_pb : in std_logic;
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start_pb : in std_logic;
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ready_pb : out std_logic;
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ready_pb : out std_logic;
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zig_sm_settings : in T_SM_SETTINGS;
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zig_sm_settings : in T_SM_SETTINGS;
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|
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-- RLE
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-- Quantizer
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rle_buf_sel : in std_logic;
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qua_buf_sel : in std_logic;
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rle_rdaddr : in std_logic_vector(5 downto 0);
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qua_rdaddr : in std_logic_vector(5 downto 0);
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rle_data : out std_logic_vector(11 downto 0);
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qua_data : out std_logic_vector(11 downto 0);
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|
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-- FDCT
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-- FDCT
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fdct_buf_sel : out std_logic;
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fdct_buf_sel : out std_logic;
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fdct_rd_addr : out std_logic_vector(5 downto 0);
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fdct_rd_addr : out std_logic_vector(5 downto 0);
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fdct_data : in std_logic_vector(11 downto 0);
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fdct_data : in std_logic_vector(11 downto 0);
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fdct_rden : out std_logic;
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fdct_rden : out std_logic
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|
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-- HOST
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qdata : in std_logic_vector(7 downto 0);
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qaddr : in std_logic_vector(6 downto 0);
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qwren : in std_logic
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|
);
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);
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end entity ZZ_TOP;
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end entity ZZ_TOP;
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|
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 83... |
Line 78... |
signal dbuf_raddr : std_logic_vector(6 downto 0);
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signal dbuf_raddr : std_logic_vector(6 downto 0);
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signal zigzag_di : std_logic_vector(11 downto 0);
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signal zigzag_di : std_logic_vector(11 downto 0);
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signal zigzag_divalid : std_logic;
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signal zigzag_divalid : std_logic;
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signal zigzag_dout : std_logic_vector(11 downto 0);
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signal zigzag_dout : std_logic_vector(11 downto 0);
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signal zigzag_dovalid : std_logic;
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signal zigzag_dovalid : std_logic;
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signal quant_dout : std_logic_vector(11 downto 0);
|
|
signal quant_dovalid : std_logic;
|
|
signal wr_cnt : unsigned(5 downto 0);
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signal wr_cnt : unsigned(5 downto 0);
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signal rd_cnt : unsigned(5 downto 0);
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signal rd_cnt : unsigned(5 downto 0);
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signal rd_en_d : std_logic_vector(5 downto 0);
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signal rd_en_d : std_logic_vector(5 downto 0);
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signal rd_en : std_logic;
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signal rd_en : std_logic;
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signal fdct_buf_sel_s : std_logic;
|
signal fdct_buf_sel_s : std_logic;
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| Line 100... |
Line 93... |
-- Architecture: begin
|
-- Architecture: begin
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
begin
|
begin
|
|
|
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
|
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
|
rle_data <= dbuf_q;
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qua_data <= dbuf_q;
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fdct_buf_sel <= fdct_buf_sel_s;
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fdct_buf_sel <= fdct_buf_sel_s;
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fdct_rden <= rd_en;
|
fdct_rden <= rd_en;
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- ZigZag Core
|
-- ZigZag Core
|
| Line 132... |
Line 125... |
|
|
zigzag_di <= fdct_data;
|
zigzag_di <= fdct_data;
|
zigzag_divalid <= rd_en_d(1);
|
zigzag_divalid <= rd_en_d(1);
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- Quantizer
|
|
-------------------------------------------------------------------
|
|
U_quantizer : entity work.quantizer
|
|
generic map
|
|
(
|
|
SIZE_C => 12,
|
|
RAMQADDR_W => 7,
|
|
RAMQDATA_W => 8
|
|
)
|
|
port map
|
|
(
|
|
rst => RST,
|
|
clk => CLK,
|
|
di => zigzag_dout,
|
|
divalid => zigzag_dovalid,
|
|
qdata => qdata,
|
|
qwaddr => qaddr,
|
|
qwren => qwren,
|
|
cmp_idx => zig_sm_settings.cmp_idx,
|
|
|
|
do => quant_dout,
|
|
dovalid => quant_dovalid
|
|
);
|
|
|
|
-------------------------------------------------------------------
|
|
-- DBUF
|
-- DBUF
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
U_RAMZ : entity work.RAMZ
|
U_RAMZ : entity work.RAMZ
|
generic map
|
generic map
|
(
|
(
|
| Line 176... |
Line 144... |
clk => CLK,
|
clk => CLK,
|
|
|
q => dbuf_q
|
q => dbuf_q
|
);
|
);
|
|
|
dbuf_data <= quant_dout;
|
dbuf_data <= zigzag_dout;
|
dbuf_waddr <= (not rle_buf_sel) & std_logic_vector(wr_cnt);
|
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
|
dbuf_we <= quant_dovalid;
|
dbuf_we <= zigzag_dovalid;
|
dbuf_raddr <= rle_buf_sel & rle_rdaddr;
|
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- FIFO Ctrl
|
-- FIFO Ctrl
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
p_fifo_ctrl : process(CLK, RST)
|
p_fifo_ctrl : process(CLK, RST)
|
| Line 241... |
Line 209... |
|
|
if start_pb = '1' then
|
if start_pb = '1' then
|
wr_cnt <= (others => '0');
|
wr_cnt <= (others => '0');
|
end if;
|
end if;
|
|
|
if quant_dovalid = '1' then
|
if zigzag_dovalid = '1' then
|
if wr_cnt = 64-1 then
|
if wr_cnt = 64-1 then
|
wr_cnt <= (others => '0');
|
wr_cnt <= (others => '0');
|
ready_pb <= '1';
|
|
else
|
else
|
wr_cnt <=wr_cnt + 1;
|
wr_cnt <=wr_cnt + 1;
|
end if;
|
end if;
|
|
|
|
-- give ready ahead to save cycles!
|
|
if wr_cnt = 64-1-3 then
|
|
ready_pb <= '1';
|
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
