| Line 38... |
Line 38... |
port
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port
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(
|
(
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rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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divalid : in STD_LOGIC;
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start_pb : in std_logic;
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start_pb : in std_logic;
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sof : in std_logic;
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sof : in std_logic;
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rle_sm_settings : in T_SM_SETTINGS;
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rle_sm_settings : in T_SM_SETTINGS;
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|
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runlength : out STD_LOGIC_VECTOR(3 downto 0);
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runlength : out STD_LOGIC_VECTOR(3 downto 0);
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size : out STD_LOGIC_VECTOR(3 downto 0);
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size : out STD_LOGIC_VECTOR(3 downto 0);
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amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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dovalid : out STD_LOGIC
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dovalid : out STD_LOGIC;
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rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
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);
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);
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end rle;
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end rle;
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|
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architecture rtl of rle is
|
architecture rtl of rle is
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|
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| Line 65... |
Line 65... |
signal acc_reg : SIGNED(RAMDATA_W downto 0);
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signal acc_reg : SIGNED(RAMDATA_W downto 0);
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signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);
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signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);
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signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);
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signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);
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signal runlength_reg : UNSIGNED(3 downto 0);
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signal runlength_reg : UNSIGNED(3 downto 0);
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signal dovalid_reg : STD_LOGIC;
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signal dovalid_reg : STD_LOGIC;
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signal zero_cnt : unsigned(3 downto 0);
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signal zero_cnt : unsigned(5 downto 0);
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signal wr_cnt_d1 : unsigned(5 downto 0);
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signal wr_cnt_d1 : unsigned(5 downto 0);
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signal wr_cnt : unsigned(5 downto 0);
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signal wr_cnt : unsigned(5 downto 0);
|
|
|
|
signal rd_cnt : unsigned(5 downto 0);
|
|
signal rd_en : std_logic;
|
|
|
|
signal divalid : STD_LOGIC;
|
|
signal zrl_proc : std_logic;
|
|
signal zrl_proc_d1 : std_logic;
|
|
signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
begin
|
begin
|
|
|
size <= STD_LOGIC_VECTOR(size_reg);
|
size <= STD_LOGIC_VECTOR(size_reg);
|
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
|
amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
|
|
|
|
rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
|
|
|
|
-------------------------------------------
|
|
-- Counter1
|
|
-------------------------------------------
|
|
process(clk,rst)
|
|
begin
|
|
if rst = '1' then
|
|
rd_en <= '0';
|
|
rd_cnt <= (others => '0');
|
|
elsif clk = '1' and clk'event then
|
|
if start_pb = '1' then
|
|
rd_cnt <= (others => '0');
|
|
rd_en <= '1';
|
|
end if;
|
|
|
|
-- input read enable
|
|
if rd_en = '1' and zrl_proc = '0' then
|
|
if rd_cnt = 64-1 then
|
|
rd_cnt <= (others => '0');
|
|
rd_en <= '0';
|
|
else
|
|
rd_cnt <= rd_cnt + 1;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
-------------------------------------------
|
-------------------------------------------
|
-- MAIN PROCESSING
|
-- MAIN PROCESSING
|
-------------------------------------------
|
-------------------------------------------
|
process(clk)
|
process(clk,rst)
|
begin
|
begin
|
if clk = '1' and clk'event then
|
|
if rst = '1' then
|
if rst = '1' then
|
wr_cnt_d1 <= (others => '0');
|
wr_cnt_d1 <= (others => '0');
|
prev_dc_reg_0 <= (others => '0');
|
prev_dc_reg_0 <= (others => '0');
|
prev_dc_reg_1 <= (others => '0');
|
prev_dc_reg_1 <= (others => '0');
|
prev_dc_reg_2 <= (others => '0');
|
prev_dc_reg_2 <= (others => '0');
|
| Line 91... |
Line 125... |
acc_reg <= (others => '0');
|
acc_reg <= (others => '0');
|
runlength_reg <= (others => '0');
|
runlength_reg <= (others => '0');
|
runlength <= (others => '0');
|
runlength <= (others => '0');
|
dovalid <= '0';
|
dovalid <= '0';
|
zero_cnt <= (others => '0');
|
zero_cnt <= (others => '0');
|
else
|
zrl_proc <= '0';
|
|
zrl_proc_d1 <= '0';
|
|
elsif clk = '1' and clk'event then
|
dovalid_reg <= '0';
|
dovalid_reg <= '0';
|
runlength_reg <= (others => '0');
|
runlength_reg <= (others => '0');
|
|
|
wr_cnt_d1 <= wr_cnt;
|
wr_cnt_d1 <= wr_cnt;
|
runlength <= std_logic_vector(runlength_reg);
|
runlength <= std_logic_vector(runlength_reg);
|
dovalid <= dovalid_reg;
|
dovalid <= dovalid_reg;
|
|
divalid <= rd_en;
|
|
zrl_proc_d1 <= zrl_proc;
|
|
|
-- input data valid
|
-- input data valid
|
if divalid = '1' then
|
if divalid = '1' and zrl_proc_d1 = '0' then
|
wr_cnt <= wr_cnt + 1;
|
wr_cnt <= wr_cnt + 1;
|
|
|
-- first DCT coefficient received, DC data
|
-- first DCT coefficient received, DC data
|
if wr_cnt = 0 then
|
if wr_cnt = 0 then
|
-- differental coding of DC data per component
|
-- differental coding of DC data per component
|
| Line 130... |
Line 167... |
-- EOB
|
-- EOB
|
if wr_cnt = 63 then
|
if wr_cnt = 63 then
|
acc_reg <= (others => '0');
|
acc_reg <= (others => '0');
|
runlength_reg <= (others => '0');
|
runlength_reg <= (others => '0');
|
dovalid_reg <= '1';
|
dovalid_reg <= '1';
|
-- zero extension symbol
|
-- no EOB
|
elsif zero_cnt = 15 then
|
|
acc_reg <= (others => '0');
|
|
runlength_reg <= to_unsigned(15, runlength_reg'length);
|
|
dovalid_reg <= '1';
|
|
zero_cnt <= (others => '0');
|
|
-- zero_cnt < 15 and no EOB
|
|
else
|
else
|
zero_cnt <= zero_cnt + 1;
|
zero_cnt <= zero_cnt + 1;
|
end if;
|
end if;
|
-- non-zero AC
|
-- non-zero AC
|
else
|
else
|
|
-- normal RLE case
|
|
if zero_cnt <= 15 then
|
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
|
acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);
|
runlength_reg <= zero_cnt;
|
runlength_reg <= zero_cnt(3 downto 0);
|
zero_cnt <= (others => '0');
|
zero_cnt <= (others => '0');
|
dovalid_reg <= '1';
|
dovalid_reg <= '1';
|
|
-- zero_cnt > 15
|
|
else
|
|
-- generate ZRL
|
|
acc_reg <= (others => '0');
|
|
runlength_reg <= X"F";
|
|
zero_cnt <= zero_cnt - 16;
|
|
dovalid_reg <= '1';
|
|
-- stall input until ZRL is handled
|
|
zrl_proc <= '1';
|
|
zrl_di <= di;
|
|
end if;
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
-- ZRL processing
|
|
if zrl_proc = '1' then
|
|
if zero_cnt <= 15 then
|
|
acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
|
|
runlength_reg <= zero_cnt(3 downto 0);
|
|
zero_cnt <= (others => '0');
|
|
dovalid_reg <= '1';
|
|
-- continue input handling
|
|
zrl_proc <= '0';
|
|
-- zero_cnt > 15
|
|
else
|
|
-- generate ZRL
|
|
acc_reg <= (others => '0');
|
|
runlength_reg <= X"F";
|
|
zero_cnt <= zero_cnt - 16;
|
|
dovalid_reg <= '1';
|
|
end if;
|
end if;
|
end if;
|
|
|
-- start of 8x8 block processing
|
-- start of 8x8 block processing
|
if start_pb = '1' then
|
if start_pb = '1' then
|
zero_cnt <= (others => '0');
|
zero_cnt <= (others => '0');
|
| Line 163... |
Line 226... |
prev_dc_reg_1 <= (others => '0');
|
prev_dc_reg_1 <= (others => '0');
|
prev_dc_reg_2 <= (others => '0');
|
prev_dc_reg_2 <= (others => '0');
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
|
end process;
|
end process;
|
|
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
-- Entropy Coder
|
-- Entropy Coder
|
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
