OpenCores
URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [quantizer/] [QUANTIZER.vhd] - Diff between revs 25 and 32

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 25 Rev 32
Line 1... Line 1... 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--                                                                            --
 
--                                                                            --
 
--                          V H D L    F I L E                                --
 
--                          V H D L    F I L E                                --
 
--                          COPYRIGHT (C) 2006                                --
 
--                          COPYRIGHT (C) 2006-2009                           --
 
--                                                                            --
 
--                                                                            --
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--                                                                            --
 
--                                                                            --
 
-- Title       : DIVIDER                                                      --
 
-- Title       : DIVIDER                                                      --
 
-- Design      : DCT QUANTIZER                                                --
 
-- Design      : DCT QUANTIZER                                                --
Line 14... Line 14... 
-- File        : QUANTIZER.VHD                                                --
 
-- File        : QUANTIZER.VHD                                                --
 
-- Created     : Sun Aug 27 2006                                              --
 
-- Created     : Sun Aug 27 2006                                              --
 
--                                                                            --
 
--                                                                            --
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--                                                                            --
 
--                                                                            --
 
--  Description : Pipelined DCT Quantizer                                     --
 
 
 
--  Pipeline delay: 2*SIZE_C+INTERN_PIPE_C                                    --
 
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
 
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
 
 
 
library IEEE;
 
library IEEE;
Line 28... Line 26... 
 
 
 
 
entity quantizer is
 
entity quantizer is
 
  generic
 
  generic
 
    (
 
    (
 
      SIZE_C        : INTEGER := 12;
 
      SIZE_C        : INTEGER := 12;
 
      RAMQADDR_W    : INTEGER := 6;
 
      RAMQADDR_W    : INTEGER := 7;
 
      RAMQDATA_W    : INTEGER := 8
 
      RAMQDATA_W    : INTEGER := 8
 
    );
 
    );
 
  port
 
  port
 
    (
 
    (
 
      rst        : in  STD_LOGIC;
 
      rst        : in  STD_LOGIC;
 
      clk        : in  STD_LOGIC;
 
      clk        : in  STD_LOGIC;
 
      di         : in  STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
      di         : in  STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
      divalid    : in  STD_LOGIC;
 
      divalid    : in  STD_LOGIC;
 
      qdata      : in  std_logic_vector(7 downto 0);
 
      qdata      : in  std_logic_vector(7 downto 0);
 
      qwaddr     : in  std_logic_vector(5 downto 0);
 
      qwaddr     : in  std_logic_vector(6 downto 0);
 
      qwren      : in  std_logic;
 
      qwren      : in  std_logic;
 
 
 
      cmp_idx    : in  unsigned(1 downto 0);
 
 
 
 
 
      do         : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
      do         : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
      dovalid    : out STD_LOGIC
 
      dovalid    : out STD_LOGIC
 
    );
 
    );
 
end quantizer;
 
end quantizer;
 
 
 
 
 
architecture rtl of quantizer is
 
architecture rtl of quantizer is
 
 
 
 
 
  constant INTERN_PIPE_C : INTEGER := 3;
 
  constant INTERN_PIPE_C : INTEGER := 3;
 
 
 
 
 
  signal romaddr_s     : UNSIGNED(RAMQADDR_W-1 downto 0);
 
  signal romaddr_s     : UNSIGNED(RAMQADDR_W-2 downto 0);
 
  signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0);
 
  signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0);
 
  signal romdatao_s    : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0);
 
  signal romdatao_s    : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0);
 
  signal divisor_s     : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
  signal divisor_s     : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
  signal remainder_s   : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
  signal remainder_s   : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
  signal do_s          : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
  signal do_s          : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
Line 62... Line 61... 
  signal di_d1         : std_logic_vector(SIZE_C-1 downto 0);
 
  signal di_d1         : std_logic_vector(SIZE_C-1 downto 0);
 
 
 
 
 
  signal pipeline_reg  : STD_LOGIC_VECTOR(4 downto 0);
 
  signal pipeline_reg  : STD_LOGIC_VECTOR(4 downto 0);
 
  signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0);
 
  signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0);
 
  signal do_rdiv       : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
  signal do_rdiv       : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
 
 
 
  signal table_select  : std_logic;
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  ----------------------------
 
  ----------------------------
 
  -- RAMQ
 
  -- RAMQ
 
  ----------------------------
 
  ----------------------------
Line 84... Line 85... 
      clk         => CLK,
 
      clk         => CLK,
 
 
 
 
 
      q           => romdatao_s
 
      q           => romdatao_s
 
    );
 
    );
 
 
 
 
 
  ----------------------------
 
 
 
  -- S_DIVIDER
 
 
 
  ----------------------------
 
 
 
  --U_S_DIVIDER : entity work.s_divider
 
 
 
  --  generic map
 
 
 
  --  ( 
 
 
  --     SIZE_C => SIZE_C 
 
 
  --  )            
 
 
  --  port map
 
 
 
  --  (
 
 
 
  --     rst         => rst,
 
 
 
  --     clk         => clk,
 
 
 
  --     a           => di_d1,
 
 
 
  --     d           => divisor_s,
 
 
 
  --     
 
 
  --     q           => do_s,    
 
 
  --     r           => remainder_s, -- if ever used, needs to be 1T delayed
 
 
 
  --     round       => round_s
 
 
 
  --  ); 
 
 
 
 
 
 
  divisor_s(RAMQDATA_W-1 downto 0)      <= romdatao_s;
 
  divisor_s(RAMQDATA_W-1 downto 0)      <= romdatao_s;
 
  divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');
 
  divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');
 
 
 
 
 
  r_divider : entity work.r_divider
 
  r_divider : entity work.r_divider
Line 118... Line 101... 
       d     => romdatao_s,
 
       d     => romdatao_s,
 
 
 
 
 
       q     => do_s
 
       q     => do_s
 
  ) ;
 
  ) ;
 
  do <= do_s;
 
  do <= do_s;
 
  slv_romaddr_s <= STD_LOGIC_VECTOR(romaddr_s);
 
  slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s);
 
 
 
 
 
  ------------------------------
 
  ------------------------------
 
  ---- round to nearest integer
 
  -- Quantization sub table select
 
  ------------------------------
 
  ------------------------------
 
  --process(clk)
 
  process(clk)
 
  --begin
 
  begin
 
  --  if clk = '1' and clk'event then
 
    if clk = '1' and clk'event then
 
  --    if rst = '1' then
 
      if rst = '1' then
 
  --      do <= (others => '0');
 
        table_select <= '0';
 
  --    else
 
      else
 
  --      -- round to nearest integer?
 
        -- luminance table select
 
  --      if round_s = '1' then
 
        if cmp_idx = 0 then
 
  --        -- negative number, subtract 1
 
          table_select <= '0';
 
  --        if sign_bit_pipe(sign_bit_pipe'length-1) = '1' then
 
        -- chrominance table select
 
  --          do <= STD_LOGIC_VECTOR(SIGNED(do_s)-TO_SIGNED(1,SIZE_C));
 
        else
 
  --        -- positive number, add 1
 
          table_select <= '1';
 
  --        else
 
        end if;
 
  --          do <= STD_LOGIC_VECTOR(SIGNED(do_s)+TO_SIGNED(1,SIZE_C));
 
      end if;
 
  --        end if;
 
    end if;
 
  --      else
 
  end process;
 
  --        do <= do_s;
 
 
 
  --      end if;
 
 
 
  --    end if; 
 
 
  --  end if;
 
 
 
  --end process;
 
 
 
 
 
 
 
  ----------------------------
 
  ----------------------------
 
  -- address incrementer
 
  -- address incrementer
 
  ----------------------------
 
  ----------------------------
 
  process(clk)
 
  process(clk)
Line 158... Line 136... 
        pipeline_reg  <= (OTHERS => '0');
 
        pipeline_reg  <= (OTHERS => '0');
 
        di_d1         <= (OTHERS => '0');
 
        di_d1         <= (OTHERS => '0');
 
        sign_bit_pipe <= (others => '0');
 
        sign_bit_pipe <= (others => '0');
 
      else
 
      else
 
        if divalid = '1' then
 
        if divalid = '1' then
 
          romaddr_s <= romaddr_s + TO_UNSIGNED(1,RAMQADDR_W);
 
          romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length);
 
        end if;
 
        end if;
 
 
 
 
 
        pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;
 
        pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;
 
 
 
 
 
        di_d1 <= di;
 
        di_d1 <= di;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.