| Line 32... |
Line 32... |
use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library work;
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use work.JPEG_PKG.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 46... |
Line 47... |
CLK : in std_logic;
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CLK : in std_logic;
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RST : in std_logic;
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RST : in std_logic;
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-- CTRL
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-- CTRL
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start_pb : in std_logic;
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start_pb : in std_logic;
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ready_pb : out std_logic;
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ready_pb : out std_logic;
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huf_sm_settings : in T_SM_SETTINGS;
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-- HOST IF
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-- HOST IF
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sof : in std_logic;
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sof : in std_logic;
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img_size_x : in std_logic_vector(15 downto 0);
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img_size_x : in std_logic_vector(15 downto 0);
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img_size_y : in std_logic_vector(15 downto 0);
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img_size_y : in std_logic_vector(15 downto 0);
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| Line 119... |
Line 121... |
signal VLI_size_r : std_logic_vector(3 downto 0);
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signal VLI_size_r : std_logic_vector(3 downto 0);
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signal VLI_r : std_logic_vector(11 downto 0);
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signal VLI_r : std_logic_vector(11 downto 0);
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signal rd_en_s : std_logic;
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signal rd_en_s : std_logic;
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signal pad_byte : std_logic_vector(7 downto 0);
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signal pad_byte : std_logic_vector(7 downto 0);
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signal pad_reg : std_logic;
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signal pad_reg : std_logic;
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signal VLC_CR_DC_size : std_logic_vector(3 downto 0);
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signal VLC_CR_DC : unsigned(10 downto 0);
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signal VLC_CR_AC_size : unsigned(4 downto 0);
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signal VLC_CR_AC : unsigned(15 downto 0);
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-- Architecture: begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin
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begin
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| Line 147... |
Line 153... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- DC_ROM
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-- DC_ROM Luminance
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_DC_ROM : entity work.DC_ROM
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U_DC_ROM : entity work.DC_ROM
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port map
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port map
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(
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(
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CLK => CLK,
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CLK => CLK,
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| Line 161... |
Line 167... |
VLC_DC_size => VLC_DC_size,
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VLC_DC_size => VLC_DC_size,
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VLC_DC => VLC_DC
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VLC_DC => VLC_DC
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);
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);
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- AC_ROM
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-- AC_ROM Luminance
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_AC_ROM : entity work.AC_ROM
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U_AC_ROM : entity work.AC_ROM
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port map
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port map
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(
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(
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CLK => CLK,
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CLK => CLK,
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| Line 176... |
Line 182... |
VLC_AC_size => VLC_AC_size,
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VLC_AC_size => VLC_AC_size,
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VLC_AC => VLC_AC
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VLC_AC => VLC_AC
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);
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);
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- DC_ROM Chrominance
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-------------------------------------------------------------------
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U_DC_CR_ROM : entity work.DC_CR_ROM
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port map
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(
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CLK => CLK,
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RST => RST,
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VLI_size => VLI_size,
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VLC_DC_size => VLC_CR_DC_size,
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VLC_DC => VLC_CR_DC
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);
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-------------------------------------------------------------------
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-- AC_ROM Chrominance
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-------------------------------------------------------------------
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U_AC_CR_ROM : entity work.AC_CR_ROM
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port map
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(
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CLK => CLK,
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RST => RST,
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runlength => runlength,
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VLI_size => VLI_size,
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VLC_AC_size => VLC_CR_AC_size,
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VLC_AC => VLC_CR_AC
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);
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-------------------------------------------------------------------
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-- Double Fifo
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-- Double Fifo
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_DoubleFifo : entity work.DoubleFifo
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U_DoubleFifo : entity work.DoubleFifo
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port map
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port map
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(
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(
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Line 243... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- mux for DC/AC ROM
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-- mux for DC/AC ROM Luminance/Chrominance
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_mux : process(CLK, RST)
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p_mux : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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VLC_size <= (others => '0');
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VLC_size <= (others => '0');
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VLC <= (others => '0');
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VLC <= (others => '0');
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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-- DC
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if first_rle_word = '1' then
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if first_rle_word = '1' then
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-- luminance
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if huf_sm_settings.cmp_idx = 0 then
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VLC_size <= unsigned('0' & VLC_DC_size);
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VLC_size <= unsigned('0' & VLC_DC_size);
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VLC <= resize(VLC_DC, VLC'length);
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VLC <= resize(VLC_DC, VLC'length);
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-- chrominance
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else
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VLC_size <= unsigned('0' & VLC_CR_DC_size);
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VLC <= resize(VLC_CR_DC, VLC'length);
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end if;
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-- AC
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else
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else
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-- luminance
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if huf_sm_settings.cmp_idx = 0 then
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VLC_size <= VLC_AC_size;
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VLC_size <= VLC_AC_size;
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VLC <= VLC_AC;
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VLC <= VLC_AC;
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-- chrominance
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else
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VLC_size <= VLC_CR_AC_size;
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VLC <= VLC_CR_AC;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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