| Line 39... |
Line 39... |
OPB_toutSup : out std_logic;
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OPB_toutSup : out std_logic;
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OPB_errAck : out std_logic;
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OPB_errAck : out std_logic;
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-- Quantizer RAM
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-- Quantizer RAM
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qdata : out std_logic_vector(7 downto 0);
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qdata : out std_logic_vector(7 downto 0);
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qaddr : out std_logic_vector(5 downto 0);
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qaddr : out std_logic_vector(6 downto 0);
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qwren : out std_logic;
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qwren : out std_logic;
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-- CTRL
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-- CTRL
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jpeg_ready : in std_logic;
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jpeg_ready : in std_logic;
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jpeg_busy : in std_logic;
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jpeg_busy : in std_logic;
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| Line 73... |
Line 73... |
constant C_IMAGE_SIZE_REG : std_logic_vector(31 downto 0) := X"0000_0004";
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constant C_IMAGE_SIZE_REG : std_logic_vector(31 downto 0) := X"0000_0004";
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constant C_IMAGE_RAM_ACCESS_REG : std_logic_vector(31 downto 0) := X"0000_0008";
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constant C_IMAGE_RAM_ACCESS_REG : std_logic_vector(31 downto 0) := X"0000_0008";
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constant C_ENC_STS_REG : std_logic_vector(31 downto 0) := X"0000_000C";
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constant C_ENC_STS_REG : std_logic_vector(31 downto 0) := X"0000_000C";
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constant C_COD_DATA_ADDR_REG : std_logic_vector(31 downto 0) := X"0000_0010";
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constant C_COD_DATA_ADDR_REG : std_logic_vector(31 downto 0) := X"0000_0010";
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constant C_ENC_LENGTH_REG : std_logic_vector(31 downto 0) := X"0000_0014";
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constant C_ENC_LENGTH_REG : std_logic_vector(31 downto 0) := X"0000_0014";
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constant C_QUANTIZER_RAM : std_logic_vector(31 downto 0) :=
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constant C_QUANTIZER_RAM_LUM : std_logic_vector(31 downto 0) :=
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X"0000_01" & "------00";
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X"0000_01" & "------00";
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constant C_QUANTIZER_RAM_CHR : std_logic_vector(31 downto 0) :=
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X"0000_02" & "------00";
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constant C_IMAGE_RAM : std_logic_vector(31 downto 0) :=
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constant C_IMAGE_RAM : std_logic_vector(31 downto 0) :=
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X"001" & "------------------00";
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X"001" & "------------------00";
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constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
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constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
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| Line 89... |
Line 91... |
signal cod_data_addr_reg : std_logic_vector(31 downto 0);
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signal cod_data_addr_reg : std_logic_vector(31 downto 0);
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signal enc_length_reg : std_logic_vector(31 downto 0);
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signal enc_length_reg : std_logic_vector(31 downto 0);
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signal rd_dval : std_logic;
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signal rd_dval : std_logic;
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signal data_read : std_logic_vector(31 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal quantizer_ram_q : std_logic_vector(31 downto 0);
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signal image_ram_q : std_logic_vector(31 downto 0);
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signal write_done : std_logic;
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signal write_done : std_logic;
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signal OPB_select_d : std_logic;
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signal OPB_select_d : std_logic;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-- Architecture: begin
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| Line 103... |
Line 103... |
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OPB_retry <= '0';
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OPB_retry <= '0';
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OPB_toutSup <= '0';
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OPB_toutSup <= '0';
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OPB_errAck <= '0';
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OPB_errAck <= '0';
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-- temporary!!
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quantizer_ram_q <= (others => '0');
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image_ram_q <= (others => '0');
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img_size_x <= image_size_reg(31 downto 16);
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img_size_x <= image_size_reg(31 downto 16);
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img_size_y <= image_size_reg(15 downto 0);
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img_size_y <= image_size_reg(15 downto 0);
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outram_base_addr <= cod_data_addr_reg(outram_base_addr'range);
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outram_base_addr <= cod_data_addr_reg(outram_base_addr'range);
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| Line 227... |
Line 223... |
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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if std_match(OPB_ABus, C_QUANTIZER_RAM) then
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if std_match(OPB_ABus, C_QUANTIZER_RAM_LUM) then
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qdata <= OPB_DBus_in(qdata'range);
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qdata <= OPB_DBus_in(qdata'range);
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qaddr <= OPB_ABus(qaddr'high+2 downto 2);
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qaddr <= '0' & OPB_ABus(qaddr'high+2-1 downto 2);
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qwren <= '1';
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qwren <= '1';
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write_done <= '1';
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write_done <= '1';
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end if;
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end if;
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if std_match(OPB_ABus, C_QUANTIZER_RAM_CHR) then
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qdata <= OPB_DBus_in(qdata'range);
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qaddr <= '1' & OPB_ABus(qaddr'high+2-1 downto 2);
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qwren <= '1';
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write_done <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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-- special handling of status reg
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-- special handling of status reg
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if jpeg_ready = '1' then
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if jpeg_ready = '1' then
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