| Line 54... |
Line 54... |
sof : in std_logic;
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sof : in std_logic;
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img_size_x : in std_logic_vector(15 downto 0);
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img_size_x : in std_logic_vector(15 downto 0);
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img_size_y : in std_logic_vector(15 downto 0);
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img_size_y : in std_logic_vector(15 downto 0);
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jpeg_ready : out std_logic;
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jpeg_ready : out std_logic;
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jpeg_busy : out std_logic;
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jpeg_busy : out std_logic;
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cmp_max : in std_logic_vector(1 downto 0);
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-- FDCT
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-- FDCT
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fdct_start : out std_logic;
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fdct_start : out std_logic;
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fdct_ready : in std_logic;
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fdct_ready : in std_logic;
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fdct_sm_settings : out T_SM_SETTINGS;
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fdct_sm_settings : out T_SM_SETTINGS;
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| Line 106... |
Line 105... |
architecture RTL of CtrlSM is
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architecture RTL of CtrlSM is
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constant NUM_STAGES : integer := 6;
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constant NUM_STAGES : integer := 6;
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constant CMP_MAX : std_logic_vector(2 downto 0) := "100";
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type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
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type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
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type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
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type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
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type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
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type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
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signal Reg : T_ARR_SM_SETTINGS;
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signal Reg : T_ARR_SM_SETTINGS;
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| Line 267... |
Line 268... |
-------------------------------
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-------------------------------
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-- COMP
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-- COMP
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-------------------------------
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-------------------------------
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when COMP =>
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when COMP =>
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if idle(1) = '1' and start(1) = '0' then
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if idle(1) = '1' and start(1) = '0' then
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if RSM.cmp_idx < unsigned(cmp_max) then
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if RSM.cmp_idx < unsigned(CMP_MAX) then
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start(1) <= '1';
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start(1) <= '1';
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else
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else
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RSM.cmp_idx <= (others => '0');
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RSM.cmp_idx <= (others => '0');
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RSM.x_cnt <= RSM.x_cnt + 8;
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RSM.x_cnt <= RSM.x_cnt + 16;
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main_state <= HORIZ;
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main_state <= HORIZ;
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end if;
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end if;
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end if;
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end if;
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-------------------------------
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-------------------------------
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