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Line 36... |
input valid;
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input valid;
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input [N-1:0] a; // variable - positive/negative
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input [N-1:0] a; // variable - positive/negative
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output [N :0] p; // product output
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output [N :0] p; // product output
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// FHT constant
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// FHT constant
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wire [8:0] mult_constant; // always positive
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//wire [8:0] mult_constant; // always positive
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assign mult_constant = 9'd362;
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//assign mult_constant = 9'd362;
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parameter mult_constant = 9'd362;
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reg [N-1:0] a_FF;
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reg [N-1:0] a_FF;
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always @(posedge clk)
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always @(posedge clk)
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if (!rstn) a_FF <= #1 0;
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if (!rstn) a_FF <= #1 0;
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else if (valid) a_FF <= #1 a;
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else if (valid) a_FF <= #1 a;
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Line 59... |
// N-2+1+8+1 - number of bits on the output
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// N-2+1+8+1 - number of bits on the output
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// = N+8 = [N+7:0]
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// = N+8 = [N+7:0]
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wire [N+7:0] mult_wo_sign; // mult without sign
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wire [N+7:0] mult_wo_sign; // mult without sign
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assign mult_wo_sign = b[N-2:0]*mult_constant;
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assign mult_wo_sign = b[N-2:0]*mult_constant;
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// Divide on 256 - [N+7-8:0] = [N-1:0]
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// Divided by 256 - [N+7-8:0] = [N-1:0]
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wire [N-1:0] div256; // divided 256
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wire [N-1:0] div256; // divided 256
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assign div256 = mult_wo_sign >> 8;
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assign div256 = mult_wo_sign >> 8;
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assign p = a_FF[N-1] ?
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assign p = a_FF[N-1] ?
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{1'b1,{~div256[N-1:0] + {{N-1{1'b0}},1'b1}} } :
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{1'b1,{~div256[N-1:0] + {{N-1{1'b0}},1'b1}} } :
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{1'b0, div256[N-1:0]}
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{1'b0, div256[N-1:0]}
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;
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;
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endmodule
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endmodule
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// Update Log:
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// 27 Jul. 2011
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// wire [8:0] mult_constant replaced by parameter
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