| Line 125... |
Line 125... |
signal pad_reg : std_logic;
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signal pad_reg : std_logic;
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signal VLC_CR_DC_size : std_logic_vector(3 downto 0);
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signal VLC_CR_DC_size : std_logic_vector(3 downto 0);
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signal VLC_CR_DC : unsigned(10 downto 0);
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signal VLC_CR_DC : unsigned(10 downto 0);
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signal VLC_CR_AC_size : unsigned(4 downto 0);
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signal VLC_CR_AC_size : unsigned(4 downto 0);
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signal VLC_CR_AC : unsigned(15 downto 0);
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signal VLC_CR_AC : unsigned(15 downto 0);
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signal start_pb_d1 : std_logic;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-- Architecture: begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin
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begin
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| Line 346... |
Line 347... |
ready_HFW <= '0';
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ready_HFW <= '0';
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fifo_wrt_cnt <= (others => '0');
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fifo_wrt_cnt <= (others => '0');
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fifo_wren <= '0';
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fifo_wren <= '0';
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fifo_wbyte <= (others => '0');
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fifo_wbyte <= (others => '0');
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rd_en_s <= '0';
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rd_en_s <= '0';
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start_pb_d1 <= '0';
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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fifo_wren <= '0';
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fifo_wren <= '0';
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ready_HFW <= '0';
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ready_HFW <= '0';
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rd_en_s <= '0';
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rd_en_s <= '0';
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start_pb_d1 <= start_pb;
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if start_pb = '1' then
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if start_pb_d1 = '1' then
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rd_en_s <= '1';
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rd_en_s <= '1' and not rle_fifo_empty;
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end if;
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end if;
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if HFW_running = '1' and ready_HFW = '0' then
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if HFW_running = '1' and ready_HFW = '0' then
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-- there is no at least one integer byte to write this time
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-- there is no at least one integer byte to write this time
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if num_fifo_wrs = 0 then
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if num_fifo_wrs = 0 then
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ready_HFW <= '1';
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ready_HFW <= '1';
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if state = RUN_VLI then
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if state = RUN_VLI then
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rd_en_s <= '1';
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rd_en_s <= '1' and not rle_fifo_empty;
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end if;
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end if;
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-- single byte write to FIFO
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-- single byte write to FIFO
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else
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else
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fifo_wrt_cnt <= fifo_wrt_cnt + 1;
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fifo_wrt_cnt <= fifo_wrt_cnt + 1;
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fifo_wren <= '1';
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fifo_wren <= '1';
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-- last byte write
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-- last byte write
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if fifo_wrt_cnt + 1 = num_fifo_wrs then
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if fifo_wrt_cnt + 1 = num_fifo_wrs then
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ready_HFW <= '1';
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ready_HFW <= '1';
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if state = RUN_VLI then
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if state = RUN_VLI then
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rd_en_s <= '1';
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rd_en_s <= '1' and not rle_fifo_empty;
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end if;
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end if;
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fifo_wrt_cnt <= (others => '0');
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fifo_wrt_cnt <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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| Line 423... |
Line 426... |
state <= RUN_VLC;
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state <= RUN_VLC;
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end if;
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end if;
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when RUN_VLC =>
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when RUN_VLC =>
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-- data valid DC or data valid AC
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-- data valid DC or data valid AC
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if (d_val_d2 = '1' and first_rle_word = '1') or
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if (d_val_d1 = '1' and first_rle_word = '1') or
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(d_val = '1' and first_rle_word = '0') then
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(d_val = '1' and first_rle_word = '0') then
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for i in 0 to C_M-1 loop
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for i in 0 to C_M-1 loop
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if i < to_integer(VLC_size) then
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if i < to_integer(VLC_size) then
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word_reg(C_M-1-to_integer(bit_ptr)-i) <= VLC(to_integer(VLC_size)-1-i);
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word_reg(C_M-1-to_integer(bit_ptr)-i) <= VLC(to_integer(VLC_size)-1-i);
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end if;
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end if;
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