-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File Name : ByteStuffer.vhd
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-- File Name : ByteStuffer.vhd
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--
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--
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-- Project : JPEG_ENC
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-- Project : JPEG_ENC
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--
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--
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-- Module : ByteStuffer
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-- Module : ByteStuffer
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--
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--
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-- Content : ByteStuffer
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-- Content : ByteStuffer
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--
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--
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-- Description : ByteStuffer core
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-- Description : ByteStuffer core
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--
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--
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-- Spec. :
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-- Spec. :
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--
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--
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-- Author : Michal Krepa
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-- Author : Michal Krepa
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- History :
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-- History :
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-- 20090301: (MK): Initial Creation.
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-- 20090301: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
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-- generic packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library work;
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library work;
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use work.JPEG_PKG.all;
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use work.JPEG_PKG.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity ByteStuffer is
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entity ByteStuffer is
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port
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port
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(
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(
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CLK : in std_logic;
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CLK : in std_logic;
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RST : in std_logic;
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RST : in std_logic;
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-- CTRL
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-- CTRL
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start_pb : in std_logic;
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start_pb : in std_logic;
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ready_pb : out std_logic;
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ready_pb : out std_logic;
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-- HOST IF
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-- HOST IF
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sof : in std_logic;
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sof : in std_logic;
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num_enc_bytes : out std_logic_vector(23 downto 0);
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num_enc_bytes : out std_logic_vector(23 downto 0);
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outram_base_addr : in std_logic_vector(9 downto 0);
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outram_base_addr : in std_logic_vector(9 downto 0);
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-- Huffman
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-- Huffman
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huf_buf_sel : out std_logic;
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huf_buf_sel : out std_logic;
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huf_fifo_empty : in std_logic;
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huf_fifo_empty : in std_logic;
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huf_rd_req : out std_logic;
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huf_rd_req : out std_logic;
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huf_packed_byte : in std_logic_vector(7 downto 0);
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huf_packed_byte : in std_logic_vector(7 downto 0);
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-- OUT RAM
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-- OUT RAM
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ram_byte : out std_logic_vector(7 downto 0);
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ram_byte : out std_logic_vector(7 downto 0);
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ram_wren : out std_logic;
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ram_wren : out std_logic;
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ram_wraddr : out std_logic_vector(23 downto 0)
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ram_wraddr : out std_logic_vector(23 downto 0)
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);
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);
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end entity ByteStuffer;
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end entity ByteStuffer;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of ByteStuffer is
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architecture RTL of ByteStuffer is
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signal huf_data_val : std_logic_vector(3 downto 0);
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signal huf_data_val : std_logic_vector(3 downto 0);
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signal wdata_reg : std_logic_vector(15 downto 0);
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signal wdata_reg : std_logic_vector(15 downto 0);
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signal wraddr : unsigned(23 downto 0);
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signal wraddr : unsigned(23 downto 0);
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signal wr_n_cnt : unsigned(1 downto 0);
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signal wr_n_cnt : unsigned(1 downto 0);
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signal huf_buf_sel_s : std_logic;
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signal huf_buf_sel_s : std_logic;
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signal rd_en : std_logic;
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signal rd_en : std_logic;
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signal rd_en_d1 : std_logic;
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signal rd_en_d1 : std_logic;
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signal huf_rd_req_s : std_logic;
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signal huf_rd_req_s : std_logic;
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signal latch_byte : std_logic_vector(7 downto 0);
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signal latch_byte : std_logic_vector(7 downto 0);
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signal data_valid : std_logic;
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signal data_valid : std_logic;
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signal wait_for_ndata : std_logic;
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signal wait_for_ndata : std_logic;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-- Architecture: begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin
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begin
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huf_buf_sel <= huf_buf_sel_s;
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huf_buf_sel <= huf_buf_sel_s;
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huf_rd_req <= huf_rd_req_s;
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huf_rd_req <= huf_rd_req_s;
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num_enc_bytes <= std_logic_vector(wraddr);
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- CTRL_SM
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-- CTRL_SM
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_ctrl_sm : process(CLK, RST)
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p_ctrl_sm : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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wr_n_cnt <= (others => '0');
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wr_n_cnt <= (others => '0');
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ready_pb <= '0';
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ready_pb <= '0';
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huf_rd_req_s <= '0';
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huf_rd_req_s <= '0';
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huf_data_val <= (others => '0');
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huf_data_val <= (others => '0');
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rd_en <= '0';
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rd_en <= '0';
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rd_en_d1 <= '0';
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rd_en_d1 <= '0';
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wdata_reg <= (others => '0');
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wdata_reg <= (others => '0');
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ram_wren <= '0';
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ram_wren <= '0';
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wraddr <= (others => '0');
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wraddr <= (others => '0');
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ram_wraddr <= (others => '0');
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ram_wraddr <= (others => '0');
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ram_byte <= (others => '0');
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ram_byte <= (others => '0');
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latch_byte <= (others => '0');
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latch_byte <= (others => '0');
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wait_for_ndata <= '0';
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wait_for_ndata <= '0';
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data_valid <= '0';
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data_valid <= '0';
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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huf_rd_req_s <= '0';
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huf_rd_req_s <= '0';
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ready_pb <= '0';
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ready_pb <= '0';
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huf_data_val <= huf_data_val(huf_data_val'length-2 downto 0) & huf_rd_req_s;
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huf_data_val <= huf_data_val(huf_data_val'length-2 downto 0) & huf_rd_req_s;
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rd_en_d1 <= rd_en;
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rd_en_d1 <= rd_en;
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ram_wren <= '0';
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ram_wren <= '0';
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data_valid <= '0';
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data_valid <= '0';
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if start_pb = '1' then
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if start_pb = '1' then
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rd_en <= '1';
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rd_en <= '1';
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end if;
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end if;
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-- read FIFO until it becomes empty. wait until last byte read is
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-- read FIFO until it becomes empty. wait until last byte read is
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-- serviced
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-- serviced
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if rd_en_d1 = '1' and wait_for_ndata = '0' then
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if rd_en_d1 = '1' and wait_for_ndata = '0' then
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-- FIFO empty
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-- FIFO empty
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if huf_fifo_empty = '1' then
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if huf_fifo_empty = '1' then
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rd_en <= '0';
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rd_en <= '0';
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rd_en_d1 <= '0';
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rd_en_d1 <= '0';
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ready_pb <= '1';
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ready_pb <= '1';
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else
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else
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huf_rd_req_s <= '1';
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huf_rd_req_s <= '1';
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wait_for_ndata <= '1';
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wait_for_ndata <= '1';
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end if;
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end if;
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end if;
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end if;
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-- show ahead FIFO, capture data early
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-- show ahead FIFO, capture data early
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if huf_rd_req_s = '1' then
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if huf_rd_req_s = '1' then
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latch_byte <= huf_packed_byte;
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latch_byte <= huf_packed_byte;
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data_valid <= '1';
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data_valid <= '1';
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end if;
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end if;
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if huf_data_val(1) = '1' then
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if huf_data_val(1) = '1' then
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wait_for_ndata <= '0';
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wait_for_ndata <= '0';
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end if;
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end if;
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-- data from FIFO is valid
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-- data from FIFO is valid
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if data_valid = '1' then
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if data_valid = '1' then
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-- stuffing necessary
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-- stuffing necessary
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if latch_byte = X"FF" then
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if latch_byte = X"FF" then
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-- two writes are necessary for byte stuffing
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-- two writes are necessary for byte stuffing
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wr_n_cnt <= "10";
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wr_n_cnt <= "10";
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wdata_reg <= X"FF00";
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wdata_reg <= X"FF00";
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-- no stuffing
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-- no stuffing
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else
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else
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wr_n_cnt <= "01";
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wr_n_cnt <= "01";
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wdata_reg <= X"00" & latch_byte;
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wdata_reg <= X"00" & latch_byte;
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end if;
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end if;
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end if;
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end if;
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|
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if wr_n_cnt > 0 then
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if wr_n_cnt > 0 then
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wr_n_cnt <= wr_n_cnt - 1;
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wr_n_cnt <= wr_n_cnt - 1;
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ram_wren <= '1';
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ram_wren <= '1';
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wraddr <= wraddr + 1;
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wraddr <= wraddr + 1;
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end if;
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end if;
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-- delayed to make address post-increment
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-- delayed to make address post-increment
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ram_wraddr <= std_logic_vector(wraddr);
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ram_wraddr <= std_logic_vector(wraddr);
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-- stuffing
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-- stuffing
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if wr_n_cnt = 2 then
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if wr_n_cnt = 2 then
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ram_byte <= wdata_reg(15 downto 8);
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ram_byte <= wdata_reg(15 downto 8);
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elsif wr_n_cnt = 1 then
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elsif wr_n_cnt = 1 then
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ram_byte <= wdata_reg(7 downto 0);
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ram_byte <= wdata_reg(7 downto 0);
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end if;
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end if;
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if sof = '1' then
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if sof = '1' then
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wraddr <= to_unsigned(C_HDR_SIZE,wraddr'length);
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wraddr <= to_unsigned(C_HDR_SIZE,wraddr'length);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- HUFFMAN buf_sel
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-- HUFFMAN buf_sel
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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p_huf_buf_sel : process(CLK, RST)
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p_huf_buf_sel : process(CLK, RST)
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begin
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begin
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if RST = '1' then
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if RST = '1' then
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huf_buf_sel_s <= '0';
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huf_buf_sel_s <= '0';
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elsif CLK'event and CLK = '1' then
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elsif CLK'event and CLK = '1' then
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if start_pb = '1' then
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if start_pb = '1' then
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huf_buf_sel_s <= not huf_buf_sel_s;
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huf_buf_sel_s <= not huf_buf_sel_s;
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end if;
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end if;
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end if;
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end if;
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end process;
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-------------------------------------------------------------------
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-- num_enc_bytes
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-------------------------------------------------------------------
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p_num_enc_bytes : process(CLK, RST)
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|
begin
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if RST = '1' then
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num_enc_bytes <= (others => '0');
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elsif CLK'event and CLK = '1' then
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-- plus 2 for EOI marker last bytes
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num_enc_bytes <= std_logic_vector(wraddr + 2);
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end if;
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end process;
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end process;
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end architecture RTL;
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end architecture RTL;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: end
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-- Architecture: end
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|
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