URL
https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk
Subversion Repositories mkjpeg
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 36 to Rev 37
- ↔ Reverse comparison
Rev 36 → Rev 37
/mkjpeg/trunk/tb/COMPILE.do
1,18 → 1,18
#-----------------------------------------------------------------------------# |
# # |
# M A C R O F I L E # |
# COPYRIGHT (C) 2006 # |
# COPYRIGHT (C) 2009 # |
# # |
#-----------------------------------------------------------------------------# |
#- |
#- Title : MDCT_TB.DO |
#- Design : Unsigned Pipelined Divider |
#- Design : EV_JPEG_ENC |
#- Author : Michal Krepa |
#- |
#------------------------------------------------------------------------------ |
#- |
#- File : MDCT_TB.DO |
#- Created : Sat Mar 5 2006 |
#- Created : Sat Mar 31 2009 |
#- |
#------------------------------------------------------------------------------ |
#- |
91,6 → 91,7
vcom ../design/iramif/IRAMIF.vhd |
|
# jfifgen |
vlog ../design/jfifgen/HeaderRam.v |
vcom ../design/jfifgen/JFIFGen.vhd |
|
# outmux |
/mkjpeg/trunk/tb/sim.do
2,7 → 2,7
|
vsim -t ps -lib WORK JPEG_TB -novopt |
|
mem load -infile header.hex -format hex /JPEG_TB/U_JpegEnc/U_JFIFGen/U_Header_RAM |
#mem load -infile header.hex -format hex /JPEG_TB/U_JpegEnc/U_JFIFGen/U_Header_RAM |
|
do wave.do |
radix hex |
/mkjpeg/trunk/design/JFIFGen/JFIFGen.vhd
103,6 → 103,19
signal eoi_wr : std_logic; |
signal eoi_wr_d1 : std_logic; |
|
component HeaderRam is |
port |
( |
d : in STD_LOGIC_VECTOR(7 downto 0); |
waddr : in STD_LOGIC_VECTOR(9 downto 0); |
raddr : in STD_LOGIC_VECTOR(9 downto 0); |
we : in STD_LOGIC; |
clk : in STD_LOGIC; |
|
q : out STD_LOGIC_VECTOR(7 downto 0) |
); |
end component; |
|
------------------------------------------------------------------------------- |
-- Architecture: begin |
------------------------------------------------------------------------------- |
111,12 → 124,7
------------------------------------------------------------------- |
-- Header RAM |
------------------------------------------------------------------- |
U_Header_RAM : entity work.RAMZ |
generic map |
( |
RAMADDR_W => 10, |
RAMDATA_W => 8 |
) |
U_Header_RAM : entity work.HeaderRam |
port map |
( |
d => hr_data, |
/mkjpeg/trunk/design/JFIFGen/HeaderRAM.v
0,0 → 1,21
module HeaderRam(d, waddr, raddr, we, clk, q); |
output [7:0] q; |
input [7:0] d; |
input[9:0] raddr; |
input[9:0] waddr; |
input clk, we; |
|
reg [9:0] read_addr; |
reg[7:0] mem [1023:0] /* synthesis syn_ramstyle="block_ram" */; |
|
initial $readmemh("header.hex", mem); |
|
assign q = mem[read_addr]; |
|
always @(posedge clk) begin |
if (we) |
mem[waddr] <= d; |
read_addr <= raddr; |
end |
|
endmodule |