OpenCores
URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 33 to Rev 34
    ↔ Reverse comparison
  •

Rev 33 → Rev 34

/mkjpeg/trunk/doc/JPEG.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/mkjpeg/trunk/tb/wave.do
1,6 → 1,5
onerror {resume}
quietly virtual signal -install /jpeg_tb/u_jpegenc/u_fdct { /jpeg_tb/u_jpegenc/u_fdct/dbuf_waddr(5 downto 0)} wad
quietly virtual signal -install /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider { /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/mult_out(27 downto 16)} mult_out_msb
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider HostBFM
add wave -noupdate -format Logic /jpeg_tb/u_hostbfm/clk
83,35 → 82,44
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/rst
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/sof
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_ctrlsm/img_size_x
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_ctrlsm/img_size_y
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/img_size_x
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/img_size_y
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/jpeg_ready
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/jpeg_busy
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/cmp_max
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/fdct_start
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/fdct_ready
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/fdct_sm_settings
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/zig_start
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/zig_ready
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/zig_sm_settings
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/qua_start
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/qua_ready
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/qua_sm_settings
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/rle_start
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/rle_ready
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/rle_sm_settings
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/huf_start
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/huf_ready
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/huf_sm_settings
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/bs_start
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/bs_ready
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/fdct_sm_settings
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/zig_sm_settings
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/rle_sm_settings
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/huf_sm_settings
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/bs_sm_settings
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/bs_sm_settings
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/jfif_start
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/jfif_ready
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/jfif_eoi
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/out_mux_ctrl
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/main_state
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/cmp_max
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/reg
add wave -noupdate -format Literal -expand /jpeg_tb/u_jpegenc/u_ctrlsm/rsm
add wave -noupdate -format Literal -expand /jpeg_tb/u_jpegenc/u_ctrlsm/start
add wave -noupdate -format Literal -expand /jpeg_tb/u_jpegenc/u_ctrlsm/idle
add wave -noupdate -format Literal -expand /jpeg_tb/u_jpegenc/u_ctrlsm/start_pb
add wave -noupdate -format Literal -expand /jpeg_tb/u_jpegenc/u_ctrlsm/ready_pb
add wave -noupdate -format Literal -expand /jpeg_tb/u_jpegenc/u_ctrlsm/fsm
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/start
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/idle
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/start_pb
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/ready_pb
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/fsm
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/start1_d
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_ctrlsm/rsm
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/out_mux_ctrl_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_ctrlsm/out_mux_ctrl_s2
add wave -noupdate -divider BUF_FIFO
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_buf_fifo/rst
251,150 → 259,36
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/eoi_fdct
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/bf_fifo_rd_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/wad
add wave -noupdate -divider mdct
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/rst
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/dcti
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/idv
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/odv
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/dcto
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/odv1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/dcto1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/ramdatao_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/ramraddro_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/ramwaddro_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/ramdatai_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/ramwe_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/romedatao_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/romodatao_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/romeaddro_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/romoaddro_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/rome2datao_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/romo2datao_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/rome2addro_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/romo2addro_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/odv2_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/dcto2_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/trigger2_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/trigger1_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/ramdatao1_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/ramdatao2_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/ramwe1_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/ramwe2_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/memswitchrd_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/memswitchwr_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/wmemsel_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/rmemsel_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/dataready_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/datareadyack_s
add wave -noupdate -divider dct1d
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/rst
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/dcti
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/idv
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/romedatao
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/romodatao
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/odv
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/dcto
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/romeaddro
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/romoaddro
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/ramwaddro
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/ramdatai
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/ramwe
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/wmemsel
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/databuf_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/latchbuf_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/col_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/row_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/rowr_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/inpcnt_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/dcto_1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/dcto_2
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/ramwe_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/ramwe_d1
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/ramwe_d2
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/wmemsel_reg
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/wmemsel_d1
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/wmemsel_d2
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/stage2_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/stage2_cnt_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/col_2_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/ramwaddro_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/ramwaddro_d1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/ramwaddro_d2
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/even_not_odd
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/even_not_odd_d1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/romedatao_d1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct1d/romodatao_d1
add wave -noupdate -divider dct2d
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/rst
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/ramdatao
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/dataready
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/odv
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/dcto
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/ramraddro
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/rmemsel
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/datareadyack
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/databuf_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/latchbuf_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/col_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/row_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/colram_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/rowram_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/colr_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/rowr_reg
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/rmemsel_reg
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/stage1_reg
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/stage2_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/stage2_cnt_reg
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_fdct/u_mdct/u_dct2d/dataready_2_reg
add wave -noupdate -divider ZZ_TOP
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/rst
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/start_pb
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/ready_pb
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/zig_sm_settings
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/rle_buf_sel
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/rle_rdaddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/rle_data
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/zig_sm_settings
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/qua_buf_sel
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/qua_rdaddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/qua_data
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/fdct_buf_sel
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/fdct_rd_addr
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/fdct_data
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/qdata
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/qaddr
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/qwren
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/fdct_data
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/fdct_rden
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/dbuf_data
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/dbuf_q
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/dbuf_q
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/dbuf_we
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/dbuf_waddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/dbuf_raddr
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/zigzag_di
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/zigzag_di
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/zigzag_divalid
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/zigzag_dout
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/zigzag_dout
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/zigzag_dovalid
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/quant_dout
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/quant_dovalid
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/wr_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/rd_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/rd_en_d
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/rd_en
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/fdct_buf_sel_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/rst
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/clk
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/di
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/divalid
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/rd_addr
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_rden
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_empty
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/dout
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/dovalid
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/zz_rd_addr
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_wr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_q
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_full
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_count
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_data_in
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/zz_rd_addr
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/fifo_empty
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/fifo_rden
add wave -noupdate -divider {zigzag core}
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/rst
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/clk
411,47 → 305,60
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_full
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_count
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_zigzag/fifo_data_in
add wave -noupdate -divider QUANT_TOP
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/rst
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/start_pb
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/ready_pb
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/qua_sm_settings
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/rle_buf_sel
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/rle_rdaddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/rle_data
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/zig_buf_sel
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/zig_rd_addr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/zig_data
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/qdata
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/qaddr
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/qwren
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/dbuf_data
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/dbuf_q
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/dbuf_we
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/dbuf_waddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/dbuf_raddr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/zigzag_di
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/zigzag_divalid
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/quant_dout
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/quant_dovalid
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/wr_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/rd_cnt
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/rd_en_d
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/rd_en
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/zig_buf_sel_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/zz_rd_addr
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/fifo_empty
add wave -noupdate -divider quantizer
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/rst
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/clk
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/di
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/divalid
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/qdata
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/qwaddr
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/qwren
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/cmp_idx
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/do
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/dovalid
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/romaddr_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/slv_romaddr_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/romdatao_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/divisor_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/remainder_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/do_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/round_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/di_d1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/pipeline_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/sign_bit_pipe
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/do_rdiv
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/table_select
add wave -noupdate -divider r_divider
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/rst
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/clk
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/a
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/d
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/q
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/romr_addr
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/romr_datao
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/dividend
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/dividend_d1
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/reciprocal
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/mult_out_msb
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/mult_out
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/mult_out_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/signbit
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/signbit_d1
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/signbit_d2
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_zz_top/u_quantizer/r_divider/signbit_d3
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/rst
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/clk
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/di
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/divalid
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/qdata
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/qwaddr
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/qwren
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/cmp_idx
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/do
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/dovalid
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/romaddr_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/slv_romaddr_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/romdatao_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/divisor_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/remainder_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/do_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/round_s
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/di_d1
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/pipeline_reg
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/sign_bit_pipe
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/do_rdiv
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_quant_top/u_quantizer/table_select
add wave -noupdate -divider RLE_TOP
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/rst
465,9 → 372,6
add wave -noupdate -format Literal -radix unsigned /jpeg_tb/u_jpegenc/u_rle_top/huf_amplitude
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/huf_dval
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/huf_fifo_empty
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/zig_buf_sel
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/zig_rd_addr
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/zig_data
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/dbuf_data
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_rle_top/dbuf_q
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/dbuf_we
480,7 → 384,6
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/rle_dovalid
add wave -noupdate -format Literal -radix decimal /jpeg_tb/u_jpegenc/u_rle_top/rle_di
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/rle_divalid
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/zig_buf_sel_s
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/huf_dval_p0
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rledoublefifo/clk
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_rle_top/u_rledoublefifo/rst
660,7 → 563,7
add wave -noupdate -format Logic /jpeg_tb/u_jpegenc/u_outmux/ram_wren
add wave -noupdate -format Literal /jpeg_tb/u_jpegenc/u_outmux/ram_wraddr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {45000815232 ps} 0}
WaveRestoreCursors {{Cursor 4} {444348 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 55
configure wave -justifyvalue left
675,4 → 578,4
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {45000756225 ps} {45001012831 ps}
WaveRestoreZoom {0 ps} {1050 ns}
/mkjpeg/trunk/tb/COMPILE.do
54,11 → 54,12
vcom ../tb/vhdl/DCT_TROM.vhd
 
# quantizer
vcom ../design/quantizer/ROMQ.vhd
vcom ../design/quantizer/s_divider.vhd
#vcom ../design/quantizer/ROMQ.vhd
#vcom ../design/quantizer/s_divider.vhd
vcom ../design/quantizer/ROMR.vhd
vcom ../design/quantizer/r_divider.vhd
vcom ../design/quantizer/QUANTIZER.vhd
vcom ../design/quantizer/QUANT_TOP.vhd
 
# zigzag
vcom ../design/zigzag/ZIGZAG.vhd
/mkjpeg/trunk/tb/vhdl/HostBFM.vhd
303,10 → 303,10
--X"1C", X"1E", X"1F", X"1E"
-- 75%
X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
--X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
--X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
--X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
--X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
-- 15 %
--X"35", X"25", X"28", X"2F",
327,14 → 327,14
--X"FF", X"FF", X"FF", X"FF"
-- 50%
--X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E",
--X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
--X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25",
--X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
--X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44",
--X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
--X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71",
--X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E",
X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25",
X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44",
X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71",
X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
);
constant qrom_chr : ROMQ_TYPE :=
/mkjpeg/trunk/design/control/CtrlSM.vhd
65,6 → 65,11
zig_ready : in std_logic;
zig_sm_settings : out T_SM_SETTINGS;
-- Quantizer
qua_start : out std_logic;
qua_ready : in std_logic;
qua_sm_settings : out T_SM_SETTINGS;
-- RLE
rle_start : out std_logic;
rle_ready : in std_logic;
97,16 → 102,18
-------------------------------------------------------------------------------
architecture RTL of CtrlSM is
 
constant NUM_STAGES : integer := 6;
 
type T_STATE is (IDLES, JFIF, HORIZ, COMP, VERT, EOI);
type ARR_FSM is array(5 downto 1) of std_logic_vector(1 downto 0);
type ARR_FSM is array(NUM_STAGES downto 1) of std_logic_vector(1 downto 0);
type T_ARR_SM_SETTINGS is array(6 downto 1) of T_SM_SETTINGS;
type T_ARR_SM_SETTINGS is array(NUM_STAGES+1 downto 1) of T_SM_SETTINGS;
signal Reg : T_ARR_SM_SETTINGS;
signal main_state : T_STATE;
signal start : std_logic_vector(6 downto 1);
signal idle : std_logic_vector(6 downto 1);
signal start_PB : std_logic_vector(5 downto 1);
signal ready_PB : std_logic_vector(5 downto 1);
signal start : std_logic_vector(NUM_STAGES+1 downto 1);
signal idle : std_logic_vector(NUM_STAGES+1 downto 1);
signal start_PB : std_logic_vector(NUM_STAGES downto 1);
signal ready_PB : std_logic_vector(NUM_STAGES downto 1);
signal fsm : ARR_FSM;
signal start1_d : std_logic;
signal RSM : T_SM_SETTINGS;
120,9 → 127,10
 
fdct_sm_settings <= Reg(1);
zig_sm_settings <= Reg(2);
rle_sm_settings <= Reg(3);
huf_sm_settings <= Reg(4);
bs_sm_settings <= Reg(5);
qua_sm_settings <= Reg(3);
rle_sm_settings <= Reg(4);
huf_sm_settings <= Reg(5);
bs_sm_settings <= Reg(6);
 
fdct_start <= start_PB(1);
ready_PB(1) <= fdct_ready;
130,21 → 138,24
zig_start <= start_PB(2);
ready_PB(2) <= zig_ready;
rle_start <= start_PB(3);
ready_PB(3) <= rle_ready;
qua_start <= start_PB(3);
ready_PB(3) <= qua_ready;
huf_start <= start_PB(4);
ready_PB(4) <= huf_ready;
rle_start <= start_PB(4);
ready_PB(4) <= rle_ready;
bs_start <= start_PB(5);
ready_PB(5) <= bs_ready;
huf_start <= start_PB(5);
ready_PB(5) <= huf_ready;
bs_start <= start_PB(6);
ready_PB(6) <= bs_ready;
-----------------------------------------------------------------------------
-- CTRLSM1..5
-- CTRLSM 1..NUM_STAGES
-----------------------------------------------------------------------------
G_S_CTRL_SM : for i in 1 to 5 generate
G_S_CTRL_SM : for i in 1 to NUM_STAGES generate
-- CTRLSM1..5
-- CTRLSM 1..NUM_STAGES
U_S_CTRL_SM : entity work.SingleSM
port map
(
164,12 → 175,12
);
end generate G_S_CTRL_SM;
idle(6) <= '1';
idle(NUM_STAGES+1) <= '1';
-------------------------------------------------------------------
-- Reg1
-- Regs
-------------------------------------------------------------------
G_REG_SM : for i in 1 to 5 generate
G_REG_SM : for i in 1 to NUM_STAGES generate
p_reg1 : process(CLK, RST)
begin
if RST = '1' then
272,12 → 283,11
RSM.y_cnt <= RSM.y_cnt + 8;
main_state <= HORIZ;
else
if idle(1) = '1' and idle(2) = '1' and idle(3) = '1' and
idle(4) = '1' and idle(5) = '1' then
main_state <= EOI;
jfif_eoi <= '1';
if idle(NUM_STAGES downto 1) = (NUM_STAGES-1 downto 0 => '1') then
main_state <= EOI;
jfif_eoi <= '1';
out_mux_ctrl_s <= '0';
jfif_start <= '1';
jfif_start <= '1';
end if;
end if;
/mkjpeg/trunk/design/quantizer/QUANT_TOP.VHD
0,0 → 1,233
-------------------------------------------------------------------------------
-- File Name : QUANT_TOP.vhd
--
-- Project : JPEG_ENC
--
-- Module : QUANT_TOP
--
-- Content : Quantizer Top level
--
-- Description : Quantizer Top level
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090328: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity QUANT_TOP is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
qua_sm_settings : in T_SM_SETTINGS;
-- RLE
rle_buf_sel : in std_logic;
rle_rdaddr : in std_logic_vector(5 downto 0);
rle_data : out std_logic_vector(11 downto 0);
-- ZIGZAG
zig_buf_sel : out std_logic;
zig_rd_addr : out std_logic_vector(5 downto 0);
zig_data : in std_logic_vector(11 downto 0);
-- HOST
qdata : in std_logic_vector(7 downto 0);
qaddr : in std_logic_vector(6 downto 0);
qwren : in std_logic
);
end entity QUANT_TOP;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of QUANT_TOP is
 
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal zigzag_di : std_logic_vector(11 downto 0);
signal zigzag_divalid : std_logic;
signal quant_dout : std_logic_vector(11 downto 0);
signal quant_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0);
signal rd_cnt : unsigned(5 downto 0);
signal rd_en_d : std_logic_vector(5 downto 0);
signal rd_en : std_logic;
signal zig_buf_sel_s : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal fifo_empty : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
 
zig_rd_addr <= std_logic_vector(rd_cnt);
rle_data <= dbuf_q;
zig_buf_sel <= zig_buf_sel_s;
zigzag_di <= zig_data;
zigzag_divalid <= rd_en_d(0);
-------------------------------------------------------------------
-- Quantizer
-------------------------------------------------------------------
U_quantizer : entity work.quantizer
generic map
(
SIZE_C => 12,
RAMQADDR_W => 7,
RAMQDATA_W => 8
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_di,
divalid => zigzag_divalid,
qdata => qdata,
qwaddr => qaddr,
qwren => qwren,
cmp_idx => qua_sm_settings.cmp_idx,
do => quant_dout,
dovalid => quant_dovalid
);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= quant_dout;
dbuf_waddr <= (not rle_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= quant_dovalid;
dbuf_raddr <= rle_buf_sel & rle_rdaddr;
-------------------------------------------------------------------
-- Counter1
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d <= (others => '0');
rd_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
end if;
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- wr_cnt
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
end if;
if quant_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- zig_buf_sel
-------------------------------------------------------------------
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
zig_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
zig_buf_sel_s <= not zig_buf_sel_s;
end if;
end if;
end process;
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
/mkjpeg/trunk/design/rle/RLE_TOP.VHD
60,10 → 60,10
huf_dval : out std_logic;
huf_fifo_empty : out std_logic;
-- ZIGZAG
zig_buf_sel : out std_logic;
zig_rd_addr : out std_logic_vector(5 downto 0);
zig_data : in std_logic_vector(11 downto 0);
-- Quantizer
qua_buf_sel : out std_logic;
qua_rd_addr : out std_logic_vector(5 downto 0);
qua_data : in std_logic_vector(11 downto 0);
-- HostIF
sof : in std_logic
92,7 → 92,7
signal rle_di : std_logic_vector(11 downto 0);
signal rle_divalid : std_logic;
signal zig_buf_sel_s : std_logic;
signal qua_buf_sel_s : std_logic;
signal huf_dval_p0 : std_logic;
signal wr_cnt : unsigned(5 downto 0);
102,11 → 102,11
-------------------------------------------------------------------------------
begin
 
zig_rd_addr <= std_logic_vector(rd_cnt);
qua_rd_addr <= std_logic_vector(rd_cnt);
huf_runlength <= dbuf_q(19 downto 16);
huf_size <= dbuf_q(15 downto 12);
huf_amplitude <= dbuf_q(11 downto 0);
zig_buf_sel <= zig_buf_sel_s;
qua_buf_sel <= qua_buf_sel_s;
 
-------------------------------------------------------------------
-- RLE Core
133,7 → 133,7
dovalid => rle_dovalid
);
rle_di <= zig_data;
rle_di <= qua_data;
rle_divalid <= rd_en_d(0);
-------------------------------------------------------------------
230,10 → 230,10
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
zig_buf_sel_s <= '0';
qua_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
zig_buf_sel_s <= not zig_buf_sel_s;
qua_buf_sel_s <= not qua_buf_sel_s;
end if;
end if;
end process;
/mkjpeg/trunk/design/top/JpegEnc.vhd
95,6 → 95,8
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
107,6 → 109,9
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
122,6 → 127,7
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
242,6 → 248,11
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
 
-- RLE
rle_start => rle_start,
312,23 → 323,47
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
 
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
-- Quantizer
qua_buf_sel => qua_buf_sel,
qua_rdaddr => qua_rdaddr,
qua_data => qua_data,
 
-- FDCT
fdct_buf_sel => zz_buf_sel,
fdct_rd_addr => zz_rd_addr,
fdct_data => zz_data,
fdct_rden => zz_rden,
fdct_rden => zz_rden
);
-------------------------------------------------------------------
-- Quantizer top level
-------------------------------------------------------------------
U_QUANT_TOP : entity work.QUANT_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => qua_start,
ready_pb => qua_ready,
qua_sm_settings => qua_sm_settings,
 
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
 
-- ZIGZAG
zig_buf_sel => qua_buf_sel,
zig_rd_addr => qua_rdaddr,
zig_data => qua_data,
 
-- HOST
qdata => qdata,
qaddr => qaddr,
qwren => qwren
);
);
-------------------------------------------------------------------
-- RLE TOP
-------------------------------------------------------------------
351,10 → 386,10
huf_dval => huf_dval,
huf_fifo_empty => huf_fifo_empty,
 
-- ZIGZAG
zig_buf_sel => rle_buf_sel,
zig_rd_addr => rle_rdaddr,
zig_data => rle_data,
-- Quantizer
qua_buf_sel => rle_buf_sel,
qua_rd_addr => rle_rdaddr,
qua_data => rle_data,
-- HostIF
sof => sof
/mkjpeg/trunk/design/zigzag/ZZ_TOP.VHD
7,7 → 7,7
--
-- Content : ZigZag Top level
--
-- Description : Zig Zag scan and Quantizer
-- Description : Zig Zag scan
--
-- Spec. :
--
51,21 → 51,16
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- RLE
rle_buf_sel : in std_logic;
rle_rdaddr : in std_logic_vector(5 downto 0);
rle_data : out std_logic_vector(11 downto 0);
-- Quantizer
qua_buf_sel : in std_logic;
qua_rdaddr : in std_logic_vector(5 downto 0);
qua_data : out std_logic_vector(11 downto 0);
-- FDCT
fdct_buf_sel : out std_logic;
fdct_rd_addr : out std_logic_vector(5 downto 0);
fdct_data : in std_logic_vector(11 downto 0);
fdct_rden : out std_logic;
-- HOST
qdata : in std_logic_vector(7 downto 0);
qaddr : in std_logic_vector(6 downto 0);
qwren : in std_logic
fdct_rden : out std_logic
);
end entity ZZ_TOP;
 
85,8 → 80,6
signal zigzag_divalid : std_logic;
signal zigzag_dout : std_logic_vector(11 downto 0);
signal zigzag_dovalid : std_logic;
signal quant_dout : std_logic_vector(11 downto 0);
signal quant_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0);
signal rd_cnt : unsigned(5 downto 0);
signal rd_en_d : std_logic_vector(5 downto 0);
102,7 → 95,7
begin
 
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
rle_data <= dbuf_q;
qua_data <= dbuf_q;
fdct_buf_sel <= fdct_buf_sel_s;
fdct_rden <= rd_en;
 
134,31 → 127,6
zigzag_divalid <= rd_en_d(1);
-------------------------------------------------------------------
-- Quantizer
-------------------------------------------------------------------
U_quantizer : entity work.quantizer
generic map
(
SIZE_C => 12,
RAMQADDR_W => 7,
RAMQDATA_W => 8
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_dout,
divalid => zigzag_dovalid,
qdata => qdata,
qwaddr => qaddr,
qwren => qwren,
cmp_idx => zig_sm_settings.cmp_idx,
do => quant_dout,
dovalid => quant_dovalid
);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
178,10 → 146,10
q => dbuf_q
);
dbuf_data <= quant_dout;
dbuf_waddr <= (not rle_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= quant_dovalid;
dbuf_raddr <= rle_buf_sel & rle_rdaddr;
dbuf_data <= zigzag_dout;
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= zigzag_dovalid;
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
-------------------------------------------------------------------
-- FIFO Ctrl
243,13 → 211,18
wr_cnt <= (others => '0');
end if;
if quant_dovalid = '1' then
if zigzag_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
ready_pb <= '1';
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.