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1 25 mikel262
-------------------------------------------------------------------------------
2
-- File Name : HostBFM.vhd
3
--
4
-- Project   : JPEG_ENC
5
--
6
-- Module    : HostBFM
7
--
8
-- Content   : Host BFM (Xilinx OPB v2.1)
9
--
10
-- Description : 
11
--
12
-- Spec.     : 
13
--
14
-- Author    : Michal Krepa
15
--
16
-------------------------------------------------------------------------------
17
-- History :
18
-- 20090301: (MK): Initial Creation.
19
-------------------------------------------------------------------------------
20
 
21
library ieee;
22
  use ieee.std_logic_1164.all;
23
  use ieee.numeric_std.all;
24
  use IEEE.STD_LOGIC_TEXTIO.ALL;
25
 
26
library STD;
27
  use STD.TEXTIO.ALL;
28
 
29
library work;
30
  use work.GPL_V2_Image_Pkg.ALL;
31
  use WORK.MDCT_PKG.all;
32
  use WORK.MDCTTB_PKG.all;
33
 
34
 
35
entity HostBFM is
36
  port
37
  (
38
        CLK                : in  std_logic;
39
        RST                : in  std_logic;
40
        -- OPB
41
        OPB_ABus           : out std_logic_vector(31 downto 0);
42
        OPB_BE             : out std_logic_vector(3 downto 0);
43
        OPB_DBus_in        : out std_logic_vector(31 downto 0);
44
        OPB_RNW            : out std_logic;
45
        OPB_select         : out std_logic;
46
        OPB_DBus_out       : in  std_logic_vector(31 downto 0);
47
        OPB_XferAck        : in  std_logic;
48
        OPB_retry          : in  std_logic;
49
        OPB_toutSup        : in  std_logic;
50
        OPB_errAck         : in  std_logic;
51
 
52
        -- HOST DATA
53
       iram_wdata          : out std_logic_vector(23 downto 0);
54
       iram_wren           : out std_logic;
55
       fifo_almost_full    : in  std_logic;
56
 
57
        sim_done           : out std_logic
58
    );
59
end entity HostBFM;
60
 
61
-------------------------------------------------------------------------------
62
-------------------------------------------------------------------------------
63
----------------------------------- ARCHITECTURE ------------------------------
64
-------------------------------------------------------------------------------
65
-------------------------------------------------------------------------------
66
architecture RTL of HostBFM is
67
 
68
  signal num_comps   : integer;
69
  signal addr_inc    : integer := 0;
70
-------------------------------------------------------------------------------
71
-- Architecture: begin
72
-------------------------------------------------------------------------------
73
begin
74
 
75
 
76
 
77
  -------------------------------------------------------------------
78
  -- code
79
  -------------------------------------------------------------------
80
  p_code : process
81
 
82
    -----------------------------------------------------------------
83
    -- HOST WRITE
84
    -----------------------------------------------------------------
85
    procedure host_write
86
      (
87
        signal clk         : in    std_logic;
88
        constant C_ADDR    : in    unsigned(31 downto 0);
89
        constant C_WDATA   : in    unsigned(31 downto 0);
90
 
91
        signal OPB_ABus    : out   std_logic_vector(31 downto 0);
92
        signal OPB_BE      : out   std_logic_vector(3 downto 0);
93
        signal OPB_DBus_in : out   std_logic_vector(31 downto 0);
94
        signal OPB_RNW     : out   std_logic;
95
        signal OPB_select  : out   std_logic;
96
        signal OPB_XferAck : in  std_logic
97
      ) is
98
    begin
99
      OPB_ABus    <= (others => '0');
100
      OPB_BE      <= (others => '0');
101
      OPB_DBus_in <= (others => '0');
102
      OPB_RNW     <= '0';
103
      OPB_select  <= '0';
104
 
105
      wait until rising_edge(clk);
106
 
107
      OPB_select  <= '1';
108
      OPB_ABus    <= std_logic_vector(C_ADDR);
109
      OPB_RNW     <= '0';
110
      OPB_BE      <= X"F";
111
      OPB_DBus_in <= std_logic_vector(C_WDATA);
112
 
113
      wait until rising_edge(clk);
114
 
115
      while OPB_XferAck /= '1' loop
116
        wait until rising_edge(clk);
117
      end loop;
118
 
119
      OPB_ABus    <= (others => '0');
120
      OPB_BE      <= (others => '0');
121
      OPB_DBus_in <= (others => '0');
122
      OPB_RNW     <= '0';
123
      OPB_select  <= '0';
124
 
125
      assert false
126
      report CR&"Host write access, address = " & HexImage(C_ADDR) & ",data written = " & HexImage(C_WDATA) &CR
127
      severity note;
128
 
129
      wait until rising_edge(clk);
130
 
131
    end procedure host_write;
132
 
133
    -----------------------------------------------------------------
134
    -- HOST READ
135
    -----------------------------------------------------------------
136
    procedure host_read
137
      (
138
        signal clk          : in    std_logic;
139
        constant C_ADDR     : in    unsigned(31 downto 0);
140
        variable RDATA      : out   unsigned(31 downto 0);
141
 
142
        signal OPB_ABus     : out   std_logic_vector(31 downto 0);
143
        signal OPB_BE       : out   std_logic_vector(3 downto 0);
144
        signal OPB_DBus_out : in    std_logic_vector(31 downto 0);
145
        signal OPB_RNW      : out   std_logic;
146
        signal OPB_select   : out   std_logic;
147
        signal OPB_XferAck  : in  std_logic
148
      )
149
    is
150
      variable data_r : std_logic_vector(31 downto 0);
151
    begin
152
      OPB_ABus    <= (others => '0');
153
      OPB_BE      <= (others => '0');
154
      OPB_DBus_in <= (others => '0');
155
      OPB_RNW     <= '0';
156
      OPB_select  <= '0';
157
 
158
      wait until rising_edge(clk);
159
 
160
      OPB_select  <= '1';
161
      OPB_ABus    <= std_logic_vector(C_ADDR);
162
      OPB_RNW     <= '1';
163
      OPB_BE      <= X"F";
164
 
165
      wait until rising_edge(clk);
166
 
167
      while OPB_XferAck /= '1' loop
168
        wait until rising_edge(clk);
169
      end loop;
170
 
171
      RDATA := unsigned(OPB_DBus_out);
172
      data_r := OPB_DBus_out;
173
 
174
      OPB_ABus    <= (others => '0');
175
      OPB_BE      <= (others => '0');
176
      OPB_DBus_in <= (others => '0');
177
      OPB_RNW     <= '0';
178
      OPB_select  <= '0';
179
 
180
      assert false
181
      report CR&"Host read access, address = " & HexImage(C_ADDR) & ",data read = " & HexImage(data_r) &CR
182
      severity note;
183
 
184
 
185
      wait until rising_edge(clk);
186
 
187
    end procedure host_read;
188
 
189
 
190
    --------------------------------------
191
    -- read text image data
192
    --------------------------------------
193
    procedure read_image is
194
      file infile          : TEXT open read_mode is "test.txt";
195
      constant N           : integer := 8;
196
      constant MAX_COMPS   : integer := 3;
197
      variable inline      : LINE;
198
      variable tmp_int     : INTEGER := 0;
199
      variable y_size      : INTEGER := 0;
200
      variable x_size      : INTEGER := 0;
201
      variable matrix      : I_MATRIX_TYPE;
202
      variable x_blk_cnt   : INTEGER := 0;
203
      variable y_blk_cnt   : INTEGER := 0;
204
      variable n_lines_arr : N_LINES_TYPE;
205
      variable line_n      : INTEGER := 0;
206
      variable pix_n       : INTEGER := 0;
207
      variable x_n         : INTEGER := 0;
208
      variable y_n         : INTEGER := 0;
209
      variable data_word   : unsigned(31 downto 0);
210
      variable image_line  : STD_LOGIC_VECTOR(0 to MAX_COMPS*MAX_IMAGE_SIZE_X*IP_W-1);
211
 
212
      constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
213
 
214
      variable x_cnt       : integer;
215
      variable data_word2  : unsigned(31 downto 0);
216
      variable num_comps_v : integer;
217
    begin
218
      READLINE(infile,inline);
219
      READ(inline,num_comps_v);
220
      READLINE(infile,inline);
221
      READ(inline,y_size);
222
      READLINE(infile,inline);
223
      READ(inline,x_size);
224
 
225
      num_comps <= num_comps_v;
226
 
227
      if y_size rem N > 0 then
228
        assert false
229
          report "E03: Image height dimension is not multiply of 8!"
230
          severity Failure;
231
      end if;
232
      if x_size rem N > 0 then
233
        assert false
234
          report "E03: Image width dimension is not multiply of 8!"
235
          severity Failure;
236
      end if;
237
 
238
      addr_inc <= 0;
239
 
240
      -- image size
241
      host_write(CLK, X"0000_0004", to_unsigned(x_size,16) & to_unsigned(y_size,16),
242
               OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
243
 
244
      iram_wren <= '0';
245
      for y_n in 0 to y_size-1 loop
246
        READLINE(infile,inline);
247
        HREAD(inline,image_line(0 to num_comps*x_size*IP_W-1));
248
        x_cnt := 0;
249
        for x_n in 0 to x_size-1 loop
250
          data_word := X"00" & UNSIGNED(image_line(x_cnt to x_cnt+num_comps*IP_W-1));
251
          data_word2(7 downto 0)   := data_word(23 downto 16);
252
          data_word2(15 downto 8)  := data_word(15 downto 8);
253
          data_word2(23 downto 16) := data_word(7 downto 0);
254
 
255
          iram_wren  <= '0';
256
          iram_wdata <= (others => 'X');
257
          while(fifo_almost_full = '1') loop
258
            wait until rising_edge(clk);
259
          end loop;
260
 
261 28 mikel262
          --for i in 0 to 10 loop
262 25 mikel262
          --  wait until rising_edge(clk);
263
          --end loop;
264
 
265
          iram_wren <= '1';
266
          iram_wdata <= std_logic_vector(data_word2(23 downto 0));
267
          wait until rising_edge(clk);
268
 
269
          x_cnt := x_cnt + num_comps*IP_W;
270
 
271
          addr_inc <= addr_inc + 1;
272
        end loop;
273
      end loop;
274
      iram_wren <= '0';
275
 
276
    end read_image;
277
 
278
    ------------------
279
    type ROMQ_TYPE is array (0 to 64-1)
280
            of unsigned(7 downto 0);
281
 
282 32 mikel262
  constant qrom_lum : ROMQ_TYPE :=
283 25 mikel262
  (
284
  -- 100%
285
  --others => X"01"
286
 
287
  -- 85%
288
  --X"05", X"03", X"04", X"04", 
289
  --X"04", X"03", X"05", X"04", 
290
  --X"04", X"04", X"05", X"05", 
291
  --X"05", X"06", X"07", X"0C",
292
  --X"08", X"07", X"07", X"07", 
293
  --X"07", X"0F", X"0B", X"0B", 
294
  --X"09", X"0C", X"11", X"0F", 
295
  --X"12", X"12", X"11", X"0F",
296
  --X"11", X"11", X"13", X"16", 
297
  --X"1C", X"17", X"13", X"14", 
298
  --X"1A", X"15", X"11", X"11", 
299
  --X"18", X"21", X"18", X"1A",
300
  --X"1D", X"1D", X"1F", X"1F", 
301
  --X"1F", X"13", X"17", X"22", 
302
  --X"24", X"22", X"1E", X"24", 
303
  --X"1C", X"1E", X"1F", X"1E"
304
 
305
  -- 75%
306 32 mikel262
   X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
307
   X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
308
   X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
309
   X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
310 25 mikel262
 
311
   -- 15 %
312
   --X"35", X"25", X"28", X"2F", 
313
   --X"28", X"21", X"35", X"2F", 
314
   --X"2B", X"2F", X"3C", X"39", 
315
   --X"35", X"3F", X"50", X"85", 
316
   --X"57", X"50", X"49", X"49", 
317
   --X"50", X"A3", X"75", X"7B", 
318
   --X"61", X"85", X"C1", X"AA", 
319
   --X"CB", X"C8", X"BE", X"AA", 
320
   --X"BA", X"B7", X"D5", X"F0", 
321
   --X"FF", X"FF", X"D5", X"E2", 
322
   --X"FF", X"E6", X"B7", X"BA", 
323
   --X"FF", X"FF", X"FF", X"FF", 
324
   --X"FF", X"FF", X"FF", X"FF", 
325
   --X"FF", X"CE", X"FF", X"FF", 
326
   --X"FF", X"FF", X"FF", X"FF", 
327 32 mikel262
   --X"FF", X"FF", X"FF", X"FF"      
328 25 mikel262
 
329
   -- 50%
330 32 mikel262
   --X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E", 
331
   --X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
332
   --X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25", 
333
   --X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
334
   --X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44", 
335
   --X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
336
   --X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71", 
337
   --X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
338
  );
339
 
340
  constant qrom_chr : ROMQ_TYPE :=
341
  (
342
   -- 50% for luminance! but used as chrominance, TODO!!
343 25 mikel262
   X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E",
344
   X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
345
   X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25",
346
   X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
347
   X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44",
348
   X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
349
   X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71",
350
   X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
351
  );
352
 
353
    variable data_read  : unsigned(31 downto 0);
354
    variable data_write : unsigned(31 downto 0);
355
    variable addr       : unsigned(31 downto 0);
356
 
357
 
358
  ------------------------------------------------------------------------------
359
  -- BEGIN
360
  ------------------------------------------------------------------------------
361
  begin
362
    sim_done <= '0';
363
    iram_wren <= '0';
364
 
365
    while RST /= '0' loop
366
      wait until rising_edge(clk);
367
    end loop;
368
 
369
    for i in 0 to 100 loop
370
      wait until rising_edge(clk);
371
    end loop;
372
 
373
 
374
 
375
    host_read(CLK, X"0000_0000", data_read,
376
               OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
377
 
378
 
379
    host_read(CLK, X"0000_0004", data_read,
380
               OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
381
 
382 32 mikel262
    -- write luminance quantization table 
383 25 mikel262
    for i in 0 to 64-1 loop
384 32 mikel262
      data_write := X"0000_00" & qrom_lum(i);
385 25 mikel262
      addr := X"0000_0100" + to_unsigned(4*i,32);
386
      host_write(CLK, addr, data_write,
387
               OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
388
 
389
    end loop;
390
 
391 32 mikel262
    -- write chrominance quantization table 
392
    for i in 0 to 64-1 loop
393
      data_write := X"0000_00" & qrom_chr(i);
394
      addr := X"0000_0200" + to_unsigned(4*i,32);
395
      host_write(CLK, addr, data_write,
396
               OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
397
 
398
    end loop;
399
 
400
 
401 25 mikel262
 
402
    data_write := to_unsigned(1,32) + shift_left(to_unsigned(3,32),1);
403
 
404
    -- SOF & num_comps
405
    host_write(CLK, X"0000_0000", data_write,
406
               OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
407
 
408
    -- write BUF_FIFO with bitmap
409
    read_image;
410
 
411
    -- wait until JPEG encoding is done
412
    host_read(CLK, X"0000_000C", data_read,
413
               OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
414
    while data_read /= 2 loop
415
     host_read(CLK, X"0000_000C", data_read,
416
               OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
417
    end loop;
418
 
419
    sim_done <= '1';
420
 
421
    wait;
422
 
423
  end process;
424
 
425
 
426
end architecture RTL;
427
-------------------------------------------------------------------------------
428
-- Architecture: end
429
-------------------------------------------------------------------------------

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