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[/] [mkjpeg/] [trunk/] [design/] [top/] [JpegEnc.vhd] - Blame information for rev 61

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-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project   : JPEG_ENC
--
-- Module    : JpegEnc
--
-- Content   : JPEG Encoder Top Level
--
-- Description : 
--
-- Spec.     : 
--
-- Author    : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
  use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
  port
  (
        CLK                : in  std_logic;
        RST                : in  std_logic;
 
        -- OPB
        OPB_ABus           : in  std_logic_vector(31 downto 0);
        OPB_BE             : in  std_logic_vector(3 downto 0);
        OPB_DBus_in        : in  std_logic_vector(31 downto 0);
        OPB_RNW            : in  std_logic;
        OPB_select         : in  std_logic;
        OPB_DBus_out       : out std_logic_vector(31 downto 0);
        OPB_XferAck        : out std_logic;
        OPB_retry          : out std_logic;
        OPB_toutSup        : out std_logic;
        OPB_errAck         : out std_logic;
 
        -- IMAGE RAM
        iram_wdata         : in  std_logic_vector(C_PIXEL_BITS-1 downto 0);
        iram_wren          : in  std_logic;
        iram_fifo_afull    : out std_logic;
 
        -- OUT RAM
        ram_byte           : out std_logic_vector(7 downto 0);
        ram_wren           : out std_logic;
        ram_wraddr         : out std_logic_vector(23 downto 0);
        outif_almost_full  : in  std_logic
   );
end entity JpegEnc;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
 
  signal qdata              : std_logic_vector(7 downto 0);
  signal qaddr              : std_logic_vector(6 downto 0);
  signal qwren              : std_logic;
  signal jpeg_ready         : std_logic;
  signal jpeg_busy          : std_logic;
  signal outram_base_addr   : std_logic_vector(9 downto 0);
  signal num_enc_bytes      : std_logic_vector(23 downto 0);
  signal img_size_x         : std_logic_vector(15 downto 0);
  signal img_size_y         : std_logic_vector(15 downto 0);
  signal sof                : std_logic;
  signal jpg_iram_rden      : std_logic;
  signal jpg_iram_rdaddr    : std_logic_vector(31 downto 0);
  signal jpg_iram_rdata     : std_logic_vector(23 downto 0);
  signal fdct_start         : std_logic;
  signal fdct_ready         : std_logic;
  signal zig_start          : std_logic;
  signal zig_ready          : std_logic;
  signal qua_start          : std_logic;
  signal qua_ready          : std_logic;
  signal rle_start          : std_logic;
  signal rle_ready          : std_logic;
  signal huf_start          : std_logic;
  signal huf_ready          : std_logic;
  signal bs_start           : std_logic;
  signal bs_ready           : std_logic;
  signal zz_buf_sel         : std_logic;
  signal zz_rd_addr         : std_logic_vector(5 downto 0);
  signal zz_data            : std_logic_vector(11 downto 0);
  signal rle_buf_sel        : std_logic;
  signal rle_rdaddr         : std_logic_vector(5 downto 0);
  signal rle_data           : std_logic_vector(11 downto 0);
  signal qua_buf_sel        : std_logic;
  signal qua_rdaddr         : std_logic_vector(5 downto 0);
  signal qua_data           : std_logic_vector(11 downto 0);
  signal huf_buf_sel        : std_logic;
  signal huf_rdaddr         : std_logic_vector(5 downto 0);
  signal huf_rden           : std_logic;
  signal huf_runlength      : std_logic_vector(3 downto 0);
  signal huf_size           : std_logic_vector(3 downto 0);
  signal huf_amplitude      : std_logic_vector(11 downto 0);
  signal huf_dval           : std_logic;
  signal bs_buf_sel         : std_logic;
  signal bs_fifo_empty      : std_logic;
  signal bs_rd_req          : std_logic;
  signal bs_packed_byte     : std_logic_vector(7 downto 0);
  signal huf_fifo_empty     : std_logic;
  signal zz_rden            : std_logic;
  signal fdct_sm_settings   : T_SM_SETTINGS;
  signal zig_sm_settings    : T_SM_SETTINGS;
  signal qua_sm_settings    : T_SM_SETTINGS;
  signal rle_sm_settings    : T_SM_SETTINGS;
  signal huf_sm_settings    : T_SM_SETTINGS;
  signal bs_sm_settings     : T_SM_SETTINGS;
  signal image_size_reg     : std_logic_vector(31 downto 0);
  signal jfif_ram_byte      : std_logic_vector(7 downto 0);
  signal jfif_ram_wren      : std_logic;
  signal jfif_ram_wraddr    : std_logic_vector(23 downto 0);
  signal out_mux_ctrl       : std_logic;
  signal img_size_wr        : std_logic;
  signal jfif_start         : std_logic;
  signal jfif_ready         : std_logic;
  signal bs_ram_byte        : std_logic_vector(7 downto 0);
  signal bs_ram_wren        : std_logic;
  signal bs_ram_wraddr      : std_logic_vector(23 downto 0);
  signal jfif_eoi           : std_logic;
  signal fdct_fifo_rd       : std_logic;
  signal fdct_fifo_q        : std_logic_vector(23 downto 0);
  signal fdct_fifo_hf_full  : std_logic;
 
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
 
  -------------------------------------------------------------------
  -- Host Interface
  -------------------------------------------------------------------
  U_HostIF : entity work.HostIF
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- OPB
        OPB_ABus           => OPB_ABus,
        OPB_BE             => OPB_BE,
        OPB_DBus_in        => OPB_DBus_in,
        OPB_RNW            => OPB_RNW,
        OPB_select         => OPB_select,
        OPB_DBus_out       => OPB_DBus_out,
        OPB_XferAck        => OPB_XferAck,
        OPB_retry          => OPB_retry,
        OPB_toutSup        => OPB_toutSup,
        OPB_errAck         => OPB_errAck,
 
        -- Quantizer RAM
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren,
 
        -- CTRL
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
 
        -- ByteStuffer
        outram_base_addr   => outram_base_addr,
        num_enc_bytes      => num_enc_bytes,
 
        -- global
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        img_size_wr        => img_size_wr,
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- BUF_FIFO
  -------------------------------------------------------------------
  U_BUF_FIFO : entity work.BUF_FIFO
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- HOST PROG
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof,
 
        -- HOST DATA
        iram_wren          => iram_wren,
        iram_wdata         => iram_wdata,
        fifo_almost_full   => iram_fifo_afull,
 
        -- FDCT
        fdct_fifo_rd       => fdct_fifo_rd,
        fdct_fifo_q        => fdct_fifo_q,
        fdct_fifo_hf_full  => fdct_fifo_hf_full
    );
 
  -------------------------------------------------------------------
  -- Controller
  -------------------------------------------------------------------
  U_CtrlSM : entity work.CtrlSM
  port map
  (
        CLK                => CLK,
        RST                => RST,
 
        -- output IF
        outif_almost_full  => outif_almost_full,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
 
        -- FDCT
        fdct_start         => fdct_start,
        fdct_ready         => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- ZIGZAG
        zig_start          => zig_start,
        zig_ready          => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_start          => qua_start,
        qua_ready          => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_start          => rle_start,
        rle_ready          => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- Huffman
        huf_start          => huf_start,
        huf_ready          => huf_ready,
        huf_sm_settings    => huf_sm_settings,
 
        -- ByteStuffdr
        bs_start           => bs_start,
        bs_ready           => bs_ready,
        bs_sm_settings     => bs_sm_settings,
 
        -- JFIF GEN
        jfif_start         => jfif_start,
        jfif_ready         => jfif_ready,
        jfif_eoi           => jfif_eoi,
 
        -- OUT MUX         
        out_mux_ctrl       => out_mux_ctrl
    );
 
  -------------------------------------------------------------------
  -- FDCT
  -------------------------------------------------------------------
  U_FDCT : entity work.FDCT
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => fdct_start,
        ready_pb           => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- BUF_FIFO
        bf_fifo_rd         => fdct_fifo_rd,
        bf_fifo_q          => fdct_fifo_q,
        bf_fifo_hf_full    => fdct_fifo_hf_full,
 
        -- ZIG ZAG
        zz_buf_sel         => zz_buf_sel,
        zz_rd_addr         => zz_rd_addr,
        zz_data            => zz_data,
        zz_rden            => zz_rden,
 
        -- HOST
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- ZigZag top level
  -------------------------------------------------------------------
  U_ZZ_TOP : entity work.ZZ_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => zig_start,
        ready_pb           => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_buf_sel        => qua_buf_sel,
        qua_rdaddr         => qua_rdaddr,
        qua_data           => qua_data,
 
        -- FDCT
        fdct_buf_sel       => zz_buf_sel,
        fdct_rd_addr       => zz_rd_addr,
        fdct_data          => zz_data,
        fdct_rden          => zz_rden
    );
 
  -------------------------------------------------------------------
  -- Quantizer top level
  -------------------------------------------------------------------
  U_QUANT_TOP : entity work.QUANT_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => qua_start,
        ready_pb           => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_buf_sel        => rle_buf_sel,
        rle_rdaddr         => rle_rdaddr,
        rle_data           => rle_data,
 
        -- ZIGZAG
        zig_buf_sel        => qua_buf_sel,
        zig_rd_addr        => qua_rdaddr,
        zig_data           => qua_data,
 
        -- HOST
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren
    );
 
  -------------------------------------------------------------------
  -- RLE TOP
  -------------------------------------------------------------------
  U_RLE_TOP : entity work.RLE_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => rle_start,
        ready_pb           => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- HUFFMAN
        huf_buf_sel        => huf_buf_sel,
        huf_rden           => huf_rden,
        huf_runlength      => huf_runlength,
        huf_size           => huf_size,
        huf_amplitude      => huf_amplitude,
        huf_dval           => huf_dval,
        huf_fifo_empty     => huf_fifo_empty,
 
        -- Quantizer
        qua_buf_sel        => rle_buf_sel,
        qua_rd_addr        => rle_rdaddr,
        qua_data           => rle_data,
 
        -- HostIF
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- Huffman Encoder
  -------------------------------------------------------------------
  U_Huffman : entity work.Huffman
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => huf_start,
        ready_pb           => huf_ready,
        huf_sm_settings    => huf_sm_settings,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
 
        -- RLE
        rle_buf_sel        => huf_buf_sel,
        rd_en              => huf_rden,
        runlength          => huf_runlength,
        VLI_size           => huf_size,
        VLI                => huf_amplitude,
        d_val              => huf_dval,
        rle_fifo_empty     => huf_fifo_empty,
 
        -- Byte Stuffer
        bs_buf_sel         => bs_buf_sel,
        bs_fifo_empty      => bs_fifo_empty,
        bs_rd_req          => bs_rd_req,
        bs_packed_byte     => bs_packed_byte
    );
 
 
  -------------------------------------------------------------------
  -- Byte Stuffer
  -------------------------------------------------------------------
  U_ByteStuffer : entity work.ByteStuffer
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => bs_start,
        ready_pb           => bs_ready,
 
        -- HOST IF
        sof                => sof,
        num_enc_bytes      => num_enc_bytes,
        outram_base_addr   => outram_base_addr,
 
        -- Huffman
        huf_buf_sel        => bs_buf_sel,
        huf_fifo_empty     => bs_fifo_empty,
        huf_rd_req         => bs_rd_req,
        huf_packed_byte    => bs_packed_byte,
 
        -- OUT RAM
        ram_byte           => bs_ram_byte,
        ram_wren           => bs_ram_wren,
        ram_wraddr         => bs_ram_wraddr
    );
 
  -------------------------------------------------------------------
  -- JFIF Generator
  -------------------------------------------------------------------
  U_JFIFGen : entity work.JFIFGen
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start              => jfif_start,
        ready              => jfif_ready,
        eoi                => jfif_eoi,
 
        -- ByteStuffer
        num_enc_bytes         => num_enc_bytes,
 
        -- HOST IF
        qwren              => qwren,
        qwaddr             => qaddr,
        qwdata             => qdata,
        image_size_reg     => image_size_reg,
        image_size_reg_wr  => img_size_wr,
 
        -- OUT RAM
        ram_byte           => jfif_ram_byte,
        ram_wren           => jfif_ram_wren,
        ram_wraddr         => jfif_ram_wraddr
    );
 
  image_size_reg <= img_size_x & img_size_y;
 
  -------------------------------------------------------------------
  -- OutMux
  -------------------------------------------------------------------
  U_OutMux : entity work.OutMux
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        out_mux_ctrl       => out_mux_ctrl,
 
        -- ByteStuffer
        bs_ram_byte        => bs_ram_byte,
        bs_ram_wren        => bs_ram_wren,
        bs_ram_wraddr      => bs_ram_wraddr,
        -- ByteStuffer
        jfif_ram_byte      => jfif_ram_byte,
        jfif_ram_wren      => jfif_ram_wren,
        jfif_ram_wraddr    => jfif_ram_wraddr,
 
        -- OUT RAM
        ram_byte           => ram_byte,
        ram_wren           => ram_wren,
        ram_wraddr         => ram_wraddr
    );
 
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	25	mikel262	`-------------------------------------------------------------------------------`
2			`-- File Name : JpegEnc.vhd`
3			`--`
4			`-- Project : JPEG_ENC`
5			`--`
6			`-- Module : JpegEnc`
7			`--`
8			`-- Content : JPEG Encoder Top Level`
9			`--`
10			`-- Description :`
11			`--`
12			`-- Spec. :`
13			`--`
14			`-- Author : Michal Krepa`
15			`--`
16			`-------------------------------------------------------------------------------`
17			`-- History :`
18			`-- 20090301: (MK): Initial Creation.`
19			`-------------------------------------------------------------------------------`
20
21			`-------------------------------------------------------------------------------`
22			`-------------------------------------------------------------------------------`
23			`----------------------------------- LIBRARY/PACKAGE ---------------------------`
24			`-------------------------------------------------------------------------------`
25			`-------------------------------------------------------------------------------`
26
27			`-------------------------------------------------------------------------------`
28			`-- generic packages/libraries:`
29			`-------------------------------------------------------------------------------`
30			`library ieee;`
31			`use ieee.std_logic_1164.all;`
32			`use ieee.numeric_std.all;`
33
34			`-------------------------------------------------------------------------------`
35			`-- user packages/libraries:`
36			`-------------------------------------------------------------------------------`
37			`library work;`
38			`use work.JPEG_PKG.all;`
39			`-------------------------------------------------------------------------------`
40			`-------------------------------------------------------------------------------`
41			`----------------------------------- ENTITY ------------------------------------`
42			`-------------------------------------------------------------------------------`
43			`-------------------------------------------------------------------------------`
44			`entity JpegEnc is`
45			`port`
46			`(`
47			`CLK : in std_logic;`
48			`RST : in std_logic;`
49
50			`-- OPB`
51			`OPB_ABus : in std_logic_vector(31 downto 0);`
52			`OPB_BE : in std_logic_vector(3 downto 0);`
53			`OPB_DBus_in : in std_logic_vector(31 downto 0);`
54			`OPB_RNW : in std_logic;`
55			`OPB_select : in std_logic;`
56			`OPB_DBus_out : out std_logic_vector(31 downto 0);`
57			`OPB_XferAck : out std_logic;`
58			`OPB_retry : out std_logic;`
59			`OPB_toutSup : out std_logic;`
60			`OPB_errAck : out std_logic;`
61
62			`-- IMAGE RAM`
63	49	mikel262	`iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);`
64	25	mikel262	`iram_wren : in std_logic;`
65			`iram_fifo_afull : out std_logic;`
66
67			`-- OUT RAM`
68			`ram_byte : out std_logic_vector(7 downto 0);`
69			`ram_wren : out std_logic;`
70	42	mikel262	`ram_wraddr : out std_logic_vector(23 downto 0);`
71			`outif_almost_full : in std_logic`
72	46	mikel262	`);`
73	25	mikel262	`end entity JpegEnc;`
74
75	43	mikel262
76	25	mikel262	`-------------------------------------------------------------------------------`
77			`-------------------------------------------------------------------------------`
78			`----------------------------------- ARCHITECTURE ------------------------------`
79			`-------------------------------------------------------------------------------`
80			`-------------------------------------------------------------------------------`
81			`architecture RTL of JpegEnc is`
82
83			`signal qdata : std_logic_vector(7 downto 0);`
84	32	mikel262	`signal qaddr : std_logic_vector(6 downto 0);`
85	25	mikel262	`signal qwren : std_logic;`
86			`signal jpeg_ready : std_logic;`
87			`signal jpeg_busy : std_logic;`
88			`signal outram_base_addr : std_logic_vector(9 downto 0);`
89			`signal num_enc_bytes : std_logic_vector(23 downto 0);`
90			`signal img_size_x : std_logic_vector(15 downto 0);`
91			`signal img_size_y : std_logic_vector(15 downto 0);`
92			`signal sof : std_logic;`
93			`signal jpg_iram_rden : std_logic;`
94			`signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);`
95			`signal jpg_iram_rdata : std_logic_vector(23 downto 0);`
96			`signal fdct_start : std_logic;`
97			`signal fdct_ready : std_logic;`
98			`signal zig_start : std_logic;`
99			`signal zig_ready : std_logic;`
100	34	mikel262	`signal qua_start : std_logic;`
101			`signal qua_ready : std_logic;`
102	25	mikel262	`signal rle_start : std_logic;`
103			`signal rle_ready : std_logic;`
104			`signal huf_start : std_logic;`
105			`signal huf_ready : std_logic;`
106			`signal bs_start : std_logic;`
107			`signal bs_ready : std_logic;`
108			`signal zz_buf_sel : std_logic;`
109			`signal zz_rd_addr : std_logic_vector(5 downto 0);`
110			`signal zz_data : std_logic_vector(11 downto 0);`
111			`signal rle_buf_sel : std_logic;`
112			`signal rle_rdaddr : std_logic_vector(5 downto 0);`
113			`signal rle_data : std_logic_vector(11 downto 0);`
114	34	mikel262	`signal qua_buf_sel : std_logic;`
115			`signal qua_rdaddr : std_logic_vector(5 downto 0);`
116			`signal qua_data : std_logic_vector(11 downto 0);`
117	25	mikel262	`signal huf_buf_sel : std_logic;`
118			`signal huf_rdaddr : std_logic_vector(5 downto 0);`
119			`signal huf_rden : std_logic;`
120			`signal huf_runlength : std_logic_vector(3 downto 0);`
121			`signal huf_size : std_logic_vector(3 downto 0);`
122			`signal huf_amplitude : std_logic_vector(11 downto 0);`
123			`signal huf_dval : std_logic;`
124			`signal bs_buf_sel : std_logic;`
125			`signal bs_fifo_empty : std_logic;`
126			`signal bs_rd_req : std_logic;`
127			`signal bs_packed_byte : std_logic_vector(7 downto 0);`
128			`signal huf_fifo_empty : std_logic;`
129			`signal zz_rden : std_logic;`
130			`signal fdct_sm_settings : T_SM_SETTINGS;`
131			`signal zig_sm_settings : T_SM_SETTINGS;`
132	34	mikel262	`signal qua_sm_settings : T_SM_SETTINGS;`
133	25	mikel262	`signal rle_sm_settings : T_SM_SETTINGS;`
134			`signal huf_sm_settings : T_SM_SETTINGS;`
135			`signal bs_sm_settings : T_SM_SETTINGS;`
136			`signal image_size_reg : std_logic_vector(31 downto 0);`
137			`signal jfif_ram_byte : std_logic_vector(7 downto 0);`
138			`signal jfif_ram_wren : std_logic;`
139			`signal jfif_ram_wraddr : std_logic_vector(23 downto 0);`
140			`signal out_mux_ctrl : std_logic;`
141			`signal img_size_wr : std_logic;`
142			`signal jfif_start : std_logic;`
143			`signal jfif_ready : std_logic;`
144			`signal bs_ram_byte : std_logic_vector(7 downto 0);`
145			`signal bs_ram_wren : std_logic;`
146			`signal bs_ram_wraddr : std_logic_vector(23 downto 0);`
147			`signal jfif_eoi : std_logic;`
148			`signal fdct_fifo_rd : std_logic;`
149			`signal fdct_fifo_q : std_logic_vector(23 downto 0);`
150			`signal fdct_fifo_hf_full : std_logic;`
151
152			`-------------------------------------------------------------------------------`
153			`-- Architecture: begin`
154			`-------------------------------------------------------------------------------`
155			`begin`
156
157			`-------------------------------------------------------------------`
158			`-- Host Interface`
159			`-------------------------------------------------------------------`
160			`U_HostIF : entity work.HostIF`
161			`port map`
162			`(`
163			`CLK => CLK,`
164			`RST => RST,`
165			`-- OPB`
166			`OPB_ABus => OPB_ABus,`
167			`OPB_BE => OPB_BE,`
168			`OPB_DBus_in => OPB_DBus_in,`
169			`OPB_RNW => OPB_RNW,`
170			`OPB_select => OPB_select,`
171			`OPB_DBus_out => OPB_DBus_out,`
172			`OPB_XferAck => OPB_XferAck,`
173			`OPB_retry => OPB_retry,`
174			`OPB_toutSup => OPB_toutSup,`
175			`OPB_errAck => OPB_errAck,`
176
177			`-- Quantizer RAM`
178			`qdata => qdata,`
179			`qaddr => qaddr,`
180			`qwren => qwren,`
181
182			`-- CTRL`
183			`jpeg_ready => jpeg_ready,`
184			`jpeg_busy => jpeg_busy,`
185
186			`-- ByteStuffer`
187			`outram_base_addr => outram_base_addr,`
188			`num_enc_bytes => num_enc_bytes,`
189
190			`-- global`
191			`img_size_x => img_size_x,`
192			`img_size_y => img_size_y,`
193			`img_size_wr => img_size_wr,`
194	61	mikel262	`sof => sof`
195	25	mikel262	`);`
196
197			`-------------------------------------------------------------------`
198			`-- BUF_FIFO`
199			`-------------------------------------------------------------------`
200			`U_BUF_FIFO : entity work.BUF_FIFO`
201			`port map`
202			`(`
203			`CLK => CLK,`
204			`RST => RST,`
205			`-- HOST PROG`
206			`img_size_x => img_size_x,`
207			`img_size_y => img_size_y,`
208			`sof => sof,`
209
210			`-- HOST DATA`
211			`iram_wren => iram_wren,`
212			`iram_wdata => iram_wdata,`
213			`fifo_almost_full => iram_fifo_afull,`
214
215			`-- FDCT`
216			`fdct_fifo_rd => fdct_fifo_rd,`
217			`fdct_fifo_q => fdct_fifo_q,`
218			`fdct_fifo_hf_full => fdct_fifo_hf_full`
219			`);`
220
221			`-------------------------------------------------------------------`
222			`-- Controller`
223			`-------------------------------------------------------------------`
224			`U_CtrlSM : entity work.CtrlSM`
225			`port map`
226			`(`
227			`CLK => CLK,`
228			`RST => RST,`
229	42	mikel262
230			`-- output IF`
231			`outif_almost_full => outif_almost_full,`
232	25	mikel262
233			`-- HOST IF`
234			`sof => sof,`
235			`img_size_x => img_size_x,`
236			`img_size_y => img_size_y,`
237			`jpeg_ready => jpeg_ready,`
238			`jpeg_busy => jpeg_busy,`
239
240			`-- FDCT`
241			`fdct_start => fdct_start,`
242			`fdct_ready => fdct_ready,`
243			`fdct_sm_settings => fdct_sm_settings,`
244
245			`-- ZIGZAG`
246			`zig_start => zig_start,`
247			`zig_ready => zig_ready,`
248			`zig_sm_settings => zig_sm_settings,`
249	34	mikel262
250			`-- Quantizer`
251			`qua_start => qua_start,`
252			`qua_ready => qua_ready,`
253			`qua_sm_settings => qua_sm_settings,`
254	25	mikel262
255			`-- RLE`
256			`rle_start => rle_start,`
257			`rle_ready => rle_ready,`
258			`rle_sm_settings => rle_sm_settings,`
259
260			`-- Huffman`
261			`huf_start => huf_start,`
262			`huf_ready => huf_ready,`
263			`huf_sm_settings => huf_sm_settings,`
264
265			`-- ByteStuffdr`
266			`bs_start => bs_start,`
267			`bs_ready => bs_ready,`
268			`bs_sm_settings => bs_sm_settings,`
269
270			`-- JFIF GEN`
271			`jfif_start => jfif_start,`
272			`jfif_ready => jfif_ready,`
273			`jfif_eoi => jfif_eoi,`
274
275			`-- OUT MUX`
276			`out_mux_ctrl => out_mux_ctrl`
277			`);`
278
279			`-------------------------------------------------------------------`
280			`-- FDCT`
281			`-------------------------------------------------------------------`
282			`U_FDCT : entity work.FDCT`
283			`port map`
284			`(`
285			`CLK => CLK,`
286			`RST => RST,`
287			`-- CTRL`
288			`start_pb => fdct_start,`
289			`ready_pb => fdct_ready,`
290			`fdct_sm_settings => fdct_sm_settings,`
291
292			`-- BUF_FIFO`
293			`bf_fifo_rd => fdct_fifo_rd,`
294			`bf_fifo_q => fdct_fifo_q,`
295			`bf_fifo_hf_full => fdct_fifo_hf_full,`
296
297			`-- ZIG ZAG`
298			`zz_buf_sel => zz_buf_sel,`
299			`zz_rd_addr => zz_rd_addr,`
300			`zz_data => zz_data,`
301			`zz_rden => zz_rden,`
302
303			`-- HOST`
304			`img_size_x => img_size_x,`
305			`img_size_y => img_size_y,`
306			`sof => sof`
307			`);`
308
309			`-------------------------------------------------------------------`
310			`-- ZigZag top level`
311			`-------------------------------------------------------------------`
312			`U_ZZ_TOP : entity work.ZZ_TOP`
313			`port map`
314			`(`
315			`CLK => CLK,`
316			`RST => RST,`
317			`-- CTRL`
318			`start_pb => zig_start,`
319			`ready_pb => zig_ready,`
320	32	mikel262	`zig_sm_settings => zig_sm_settings,`
321	25	mikel262
322	34	mikel262	`-- Quantizer`
323			`qua_buf_sel => qua_buf_sel,`
324			`qua_rdaddr => qua_rdaddr,`
325			`qua_data => qua_data,`
326	25	mikel262
327			`-- FDCT`
328			`fdct_buf_sel => zz_buf_sel,`
329			`fdct_rd_addr => zz_rd_addr,`
330			`fdct_data => zz_data,`
331	34	mikel262	`fdct_rden => zz_rden`
332			`);`
333
334			`-------------------------------------------------------------------`
335			`-- Quantizer top level`
336			`-------------------------------------------------------------------`
337			`U_QUANT_TOP : entity work.QUANT_TOP`
338			`port map`
339			`(`
340			`CLK => CLK,`
341			`RST => RST,`
342			`-- CTRL`
343			`start_pb => qua_start,`
344			`ready_pb => qua_ready,`
345			`qua_sm_settings => qua_sm_settings,`
346	25	mikel262
347	34	mikel262	`-- RLE`
348			`rle_buf_sel => rle_buf_sel,`
349			`rle_rdaddr => rle_rdaddr,`
350			`rle_data => rle_data,`
351
352			`-- ZIGZAG`
353			`zig_buf_sel => qua_buf_sel,`
354			`zig_rd_addr => qua_rdaddr,`
355			`zig_data => qua_data,`
356
357	25	mikel262	`-- HOST`
358			`qdata => qdata,`
359			`qaddr => qaddr,`
360			`qwren => qwren`
361	34	mikel262	`);`
362
363	25	mikel262	`-------------------------------------------------------------------`
364			`-- RLE TOP`
365			`-------------------------------------------------------------------`
366			`U_RLE_TOP : entity work.RLE_TOP`
367			`port map`
368			`(`
369			`CLK => CLK,`
370			`RST => RST,`
371			`-- CTRL`
372			`start_pb => rle_start,`
373			`ready_pb => rle_ready,`
374			`rle_sm_settings => rle_sm_settings,`
375
376			`-- HUFFMAN`
377			`huf_buf_sel => huf_buf_sel,`
378			`huf_rden => huf_rden,`
379			`huf_runlength => huf_runlength,`
380			`huf_size => huf_size,`
381			`huf_amplitude => huf_amplitude,`
382			`huf_dval => huf_dval,`
383			`huf_fifo_empty => huf_fifo_empty,`
384
385	34	mikel262	`-- Quantizer`
386			`qua_buf_sel => rle_buf_sel,`
387			`qua_rd_addr => rle_rdaddr,`
388			`qua_data => rle_data,`
389	25	mikel262
390			`-- HostIF`
391			`sof => sof`
392			`);`
393
394			`-------------------------------------------------------------------`
395			`-- Huffman Encoder`
396			`-------------------------------------------------------------------`
397			`U_Huffman : entity work.Huffman`
398			`port map`
399			`(`
400			`CLK => CLK,`
401			`RST => RST,`
402			`-- CTRL`
403			`start_pb => huf_start,`
404			`ready_pb => huf_ready,`
405	36	mikel262	`huf_sm_settings => huf_sm_settings,`
406	25	mikel262
407			`-- HOST IF`
408			`sof => sof,`
409			`img_size_x => img_size_x,`
410			`img_size_y => img_size_y,`
411
412			`-- RLE`
413			`rle_buf_sel => huf_buf_sel,`
414			`rd_en => huf_rden,`
415			`runlength => huf_runlength,`
416			`VLI_size => huf_size,`
417			`VLI => huf_amplitude,`
418			`d_val => huf_dval,`
419			`rle_fifo_empty => huf_fifo_empty,`
420
421			`-- Byte Stuffer`
422			`bs_buf_sel => bs_buf_sel,`
423			`bs_fifo_empty => bs_fifo_empty,`
424			`bs_rd_req => bs_rd_req,`
425			`bs_packed_byte => bs_packed_byte`
426			`);`
427
428
429			`-------------------------------------------------------------------`
430			`-- Byte Stuffer`
431			`-------------------------------------------------------------------`
432			`U_ByteStuffer : entity work.ByteStuffer`
433			`port map`
434			`(`
435			`CLK => CLK,`
436			`RST => RST,`
437			`-- CTRL`
438			`start_pb => bs_start,`
439			`ready_pb => bs_ready,`
440
441			`-- HOST IF`
442			`sof => sof,`
443			`num_enc_bytes => num_enc_bytes,`
444			`outram_base_addr => outram_base_addr,`
445
446			`-- Huffman`
447			`huf_buf_sel => bs_buf_sel,`
448			`huf_fifo_empty => bs_fifo_empty,`
449			`huf_rd_req => bs_rd_req,`
450			`huf_packed_byte => bs_packed_byte,`
451
452			`-- OUT RAM`
453			`ram_byte => bs_ram_byte,`
454			`ram_wren => bs_ram_wren,`
455			`ram_wraddr => bs_ram_wraddr`
456			`);`
457
458			`-------------------------------------------------------------------`
459			`-- JFIF Generator`
460			`-------------------------------------------------------------------`
461			`U_JFIFGen : entity work.JFIFGen`
462			`port map`
463			`(`
464			`CLK => CLK,`
465			`RST => RST,`
466			`-- CTRL`
467			`start => jfif_start,`
468			`ready => jfif_ready,`
469			`eoi => jfif_eoi,`
470
471			`-- ByteStuffer`
472			`num_enc_bytes => num_enc_bytes,`
473
474			`-- HOST IF`
475			`qwren => qwren,`
476			`qwaddr => qaddr,`
477			`qwdata => qdata,`
478			`image_size_reg => image_size_reg,`
479			`image_size_reg_wr => img_size_wr,`
480
481			`-- OUT RAM`
482			`ram_byte => jfif_ram_byte,`
483			`ram_wren => jfif_ram_wren,`
484			`ram_wraddr => jfif_ram_wraddr`
485			`);`
486
487			`image_size_reg <= img_size_x & img_size_y;`
488
489			`-------------------------------------------------------------------`
490			`-- OutMux`
491			`-------------------------------------------------------------------`
492			`U_OutMux : entity work.OutMux`
493			`port map`
494			`(`
495			`CLK => CLK,`
496			`RST => RST,`
497			`-- CTRL`
498			`out_mux_ctrl => out_mux_ctrl,`
499
500			`-- ByteStuffer`

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