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mikel262 |
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-- --
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-- V H D L F I L E --
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-- COPYRIGHT (C) 2006 --
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-- --
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--------------------------------------------------------------------------------
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-- --
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-- Title : RAM --
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-- Design : MDCT --
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-- Author : Michal Krepa -- -- --
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-- --
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--------------------------------------------------------------------------------
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--
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-- File : RAM.VHD
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-- Created : Sat Mar 5 7:37 2006
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--
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--------------------------------------------------------------------------------
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--
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-- Description : RAM memory simulation model
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--
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-- 5:3 row select
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-- 2:0 col select
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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library WORK;
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use WORK.MDCT_PKG.all;
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entity RAM is
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port (
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d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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waddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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raddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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we : in STD_LOGIC;
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clk : in STD_LOGIC;
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q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
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);
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end RAM;
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architecture RTL of RAM is
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type mem_type is array ((2**RAMADRR_W)-1 downto 0) of
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STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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signal mem : mem_type;
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signal read_addr : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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begin
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-------------------------------------------------------------------------------
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q_sg:
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-------------------------------------------------------------------------------
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q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
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-------------------------------------------------------------------------------
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read_proc: -- register read address
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-------------------------------------------------------------------------------
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process (clk)
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begin
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if clk = '1' and clk'event then
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read_addr <= raddr;
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end if;
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end process;
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-------------------------------------------------------------------------------
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write_proc: --write access
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-------------------------------------------------------------------------------
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process (clk) begin
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if clk = '1' and clk'event then
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if we = '1' then
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mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
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end if;
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end if;
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end process;
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end RTL;
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