OpenCores
URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [huffman/] [DoubleFifo.vhd] - Blame information for rev 25

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 mikel262
-------------------------------------------------------------------------------
2
-- File Name :  DoubleFifo.vhd
3
--
4
-- Project   : JPEG_ENC
5
--
6
-- Module    : DoubleFifo
7
--
8
-- Content   : DoubleFifo
9
--
10
-- Description : 
11
--
12
-- Spec.     : 
13
--
14
-- Author    : Michal Krepa
15
--
16
-------------------------------------------------------------------------------
17
-- History :
18
-- 20090228: (MK): Initial Creation.
19
-------------------------------------------------------------------------------
20
 
21
-------------------------------------------------------------------------------
22
-------------------------------------------------------------------------------
23
----------------------------------- LIBRARY/PACKAGE ---------------------------
24
-------------------------------------------------------------------------------
25
-------------------------------------------------------------------------------
26
 
27
-------------------------------------------------------------------------------
28
-- generic packages/libraries:
29
-------------------------------------------------------------------------------
30
library ieee;
31
  use ieee.std_logic_1164.all;
32
  use ieee.numeric_std.all;
33
 
34
-------------------------------------------------------------------------------
35
-- user packages/libraries:
36
-------------------------------------------------------------------------------
37
 
38
-------------------------------------------------------------------------------
39
-------------------------------------------------------------------------------
40
----------------------------------- ENTITY ------------------------------------
41
-------------------------------------------------------------------------------
42
-------------------------------------------------------------------------------
43
entity DoubleFifo is
44
  port
45
  (
46
        CLK                : in  std_logic;
47
        RST                : in  std_logic;
48
        -- HUFFMAN
49
        data_in            : in  std_logic_vector(7 downto 0);
50
        wren               : in  std_logic;
51
        -- BYTE STUFFER
52
        buf_sel            : in  std_logic;
53
        rd_req             : in  std_logic;
54
        fifo_empty         : out std_logic;
55
        data_out           : out std_logic_vector(7 downto 0)
56
    );
57
end entity DoubleFifo;
58
 
59
-------------------------------------------------------------------------------
60
-------------------------------------------------------------------------------
61
----------------------------------- ARCHITECTURE ------------------------------
62
-------------------------------------------------------------------------------
63
-------------------------------------------------------------------------------
64
architecture RTL of DoubleFifo is
65
 
66
  signal fifo1_rd      : std_logic;
67
  signal fifo1_wr      : std_logic;
68
  signal fifo1_q       : std_logic_vector(7 downto 0);
69
  signal fifo1_full    : std_logic;
70
  signal fifo1_empty   : std_logic;
71
  signal fifo1_count   : std_logic_vector(7 downto 0);
72
 
73
  signal fifo2_rd      : std_logic;
74
  signal fifo2_wr      : std_logic;
75
  signal fifo2_q       : std_logic_vector(7 downto 0);
76
  signal fifo2_full    : std_logic;
77
  signal fifo2_empty   : std_logic;
78
  signal fifo2_count   : std_logic_vector(7 downto 0);
79
 
80
  signal fifo_data_in  : std_logic_vector(7 downto 0);
81
-------------------------------------------------------------------------------
82
-- Architecture: begin
83
-------------------------------------------------------------------------------
84
begin
85
 
86
  -------------------------------------------------------------------
87
  -- FIFO 1
88
  -------------------------------------------------------------------
89
  U_FIFO_1 : entity work.FIFO
90
  generic map
91
  (
92
        DATA_WIDTH        => 8,
93
        ADDR_WIDTH        => 7
94
  )
95
  port map
96
  (
97
        rst               => RST,
98
        clk               => CLK,
99
        rinc              => fifo1_rd,
100
        winc              => fifo1_wr,
101
        datai             => fifo_data_in,
102
 
103
        datao             => fifo1_q,
104
        fullo             => fifo1_full,
105
        emptyo            => fifo1_empty,
106
        count             => fifo1_count
107
  );
108
 
109
  -------------------------------------------------------------------
110
  -- FIFO 2
111
  -------------------------------------------------------------------
112
  U_FIFO_2 : entity work.FIFO
113
  generic map
114
  (
115
        DATA_WIDTH        => 8,
116
        ADDR_WIDTH        => 7
117
  )
118
  port map
119
  (
120
        rst               => RST,
121
        clk               => CLK,
122
        rinc              => fifo2_rd,
123
        winc              => fifo2_wr,
124
        datai             => fifo_data_in,
125
 
126
        datao             => fifo2_q,
127
        fullo             => fifo2_full,
128
        emptyo            => fifo2_empty,
129
        count             => fifo2_count
130
  );
131
 
132
  -------------------------------------------------------------------
133
  -- mux2
134
  -------------------------------------------------------------------
135
  p_mux2 : process(CLK, RST)
136
  begin
137
    if RST = '1' then
138
      fifo1_wr <= '0';
139
      fifo2_wr <= '0';
140
      fifo_data_in <= (others => '0');
141
    elsif CLK'event and CLK = '1' then
142
      if buf_sel = '0' then
143
        fifo1_wr <= wren;
144
      else
145
        fifo2_wr <= wren;
146
      end if;
147
      fifo_data_in <= data_in;
148
    end if;
149
  end process;
150
 
151
  -------------------------------------------------------------------
152
  -- mux3
153
  -------------------------------------------------------------------
154
  p_mux3 : process(CLK, RST)
155
  begin
156
    if RST = '1' then
157
      data_out   <= (others => '0');
158
      fifo1_rd   <= '0';
159
      fifo2_rd   <= '0';
160
      fifo_empty <= '0';
161
    elsif CLK'event and CLK = '1' then
162
      if buf_sel = '1' then
163
        data_out   <= fifo1_q;
164
        fifo1_rd   <= rd_req;
165
        fifo_empty <= fifo1_empty;
166
      else
167
        data_out <= fifo2_q;
168
        fifo2_rd <= rd_req;
169
        fifo_empty <= fifo2_empty;
170
      end if;
171
    end if;
172
  end process;
173
 
174
 
175
end architecture RTL;
176
-------------------------------------------------------------------------------
177
-- Architecture: end
178
-------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.