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[/] [mkjpeg/] [trunk/] [design/] [huffman/] [DC_CR_ROM.vhd] - Blame information for rev 36

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1 36 mikel262 
-------------------------------------------------------------------------------
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-- File Name :  DC_CR_ROM.vhd
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--
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-- Project   : JPEG_ENC
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--
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-- Module    : DC_CR_ROM
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--
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-- Content   : DC_CR_ROM Chrominance
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--
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-- Description :
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--
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-- Spec.     :
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--
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-- Author    : Michal Krepa
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--
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-------------------------------------------------------------------------------
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-- History :
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-- 20090329: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
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-------------------------------------------------------------------------------
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity DC_CR_ROM is
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  port
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  (
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        CLK                : in  std_logic;
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        RST                : in  std_logic;
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        VLI_size           : in  std_logic_vector(3 downto 0);
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        VLC_DC_size        : out std_logic_vector(3 downto 0);
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        VLC_DC             : out unsigned(10 downto 0)
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    );
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end entity DC_CR_ROM;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of DC_CR_ROM is
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-------------------------------------------------------------------------------
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begin
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  -------------------------------------------------------------------
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  -- DC-ROM
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  -------------------------------------------------------------------
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  p_DC_CR_ROM : process(CLK, RST)
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  begin
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    if RST = '1' then
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      VLC_DC_size <= X"0";
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      VLC_DC      <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      case VLI_size is
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        when X"0" =>
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          VLC_DC_size <= X"2";
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          VLC_DC      <= resize("00", VLC_DC'length);
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        when X"1" =>
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          VLC_DC_size <= X"2";
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          VLC_DC      <= resize("01", VLC_DC'length);
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        when X"2" =>
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          VLC_DC_size <= X"2";
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          VLC_DC      <= resize("10", VLC_DC'length);
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        when X"3" =>
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          VLC_DC_size <= X"3";
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          VLC_DC      <= resize("110", VLC_DC'length);
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        when X"4" =>
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          VLC_DC_size <= X"4";
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          VLC_DC      <= resize("1110", VLC_DC'length);
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        when X"5" =>
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          VLC_DC_size <= X"5";
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          VLC_DC      <= resize("11110", VLC_DC'length);
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        when X"6" =>
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          VLC_DC_size <= X"6";
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          VLC_DC      <= resize("111110", VLC_DC'length);
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        when X"7" =>
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          VLC_DC_size <= X"7";
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          VLC_DC      <= resize("1111110", VLC_DC'length);
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        when X"8" =>
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          VLC_DC_size <= X"8";
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          VLC_DC      <= resize("11111110", VLC_DC'length);
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        when X"9" =>
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          VLC_DC_size <= X"9";
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          VLC_DC      <= resize("111111110", VLC_DC'length);
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        when X"A" =>
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          VLC_DC_size <= X"A";
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          VLC_DC      <= resize("1111111110", VLC_DC'length);
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        when X"B" =>
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          VLC_DC_size <= X"B";
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          VLC_DC      <= resize("11111111110", VLC_DC'length);
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        when others =>
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          VLC_DC_size <= X"0";
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          VLC_DC      <= (others => '0');
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      end case;
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    end if;
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  end process;
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end architecture RTL;
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-------------------------------------------------------------------------------
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-- Architecture: end
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-------------------------------------------------------------------------------

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