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[/] [two_dimensional_fast_hartley_transform/] [trunk/] [fht_8x8_core.v] - Blame information for rev 2

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//
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// File: fht_8x8_core.v
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// Author: Ivan Rezki
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// Topic: RTL Core
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//                2-Dimensional Fast Hartley Transform
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//
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// TOP Level
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// 2D FHT 64 points -> ... clk delay
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// 
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//     +------------------------+
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//     |                        |
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// --->|    2D FHT/64 Points    |---> 
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//     |                        |
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//     +------------------------+
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//     |<---- .. clk delay ---->|
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//
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// Data is coming from somewhere (e.g. memory) with sclk one by one.
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// 1st step 1D FHT by rows:
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//                      - Shift Register for 8 points -> ... clk delay
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//                      - Alligner
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//                      - Calculate 1D FHT for 8 points. -> ... clk delay
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//                              - FF is used on the each input of the butterfly
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//                              - FF is used on the input of the multiplier
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// 2nd Step:
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// Matrix Transpose -> 64+1 clk delay
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//                      - Collecting data until 1st buffer is full as 64 points.
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//                      - Read 64 points right away after 1st buffer is full.
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//                      - At the same time 2nd buffer is ready to receive data.
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//                      - Collecting data until 2nd buffer is full as 64 points.
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//                      - Read 64 points right away after 2nd buffer is full.
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//                      - At the same time 1st buffer is ready to receive data once again.
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//                      - ...
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// 3rd Step 1D FHT by columns.
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//                      - Combine data to make 8 points in parallel. -> ... clk delay
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//                      - Calculate 1D FHT for 8 points. -> ... clk delay
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// NOTES:
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// 1. Matrix Transposition maximum data width is 16 bits.
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// ----->>> Define Multiplier Type
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//`define USE_ASIC_MULT
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//`define USE_FPGA_MULT
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// ----->>>  Define Memory Type
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//`define USE_FPGA_SPSRAM
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//`define USE_ASIC_SPSRAM
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module fht_8x8_core (
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        rstn,
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        sclk,
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        x_valid,
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        x_data,
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        fht_2d_valid,
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        fht_2d_data
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);
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// Number of input bits
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parameter N = 8;
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input   rstn;
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input   sclk;
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input                   x_valid;
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input   [N-1:0] x_data;
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output                  fht_2d_valid;
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output  [N+5:0]  fht_2d_data;
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// +++--->>> One-Dimensional Fast Hartley Transform - 1st Stage
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// Data input [N-1:0] = N bits
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// 
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wire                    fht_1d_valid;
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wire    [N+2:0]  fht_1d_data;
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fht_1d_x8 #(N) u1_fht_1d_x8_1st(
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        .rstn   (rstn),
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        .sclk   (sclk),
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        // input data
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        .x_valid        (x_valid),
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        .x_data         (x_data),
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        // output data
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        .fht_valid      (fht_1d_valid),
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        .fht_data       (fht_1d_data)
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);
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// +++--->>> Matrix Transposition <<<---+++ \\
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wire                    mem_valid;
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wire    [N+2:0]  mem_data;
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//mtx_trps_8x8_spsram #(N+3) u2_mtx_ts (
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//      .rstn           (rstn),
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//      .sclk           (sclk),
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//      
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//      .inp_valid              (fht_1d_valid),
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//      .inp_data               (fht_1d_data),
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//
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//      .mem_mux_data   (mem_data),
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//      .mem_mux_valid  (mem_valid)
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//);
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mtx_trps_8x8_dpsram #(N+3) u2_mtx_ts (
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        .rstn           (rstn),
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        .sclk           (sclk),
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        .inp_valid      (fht_1d_valid),
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        .inp_data       (fht_1d_data),
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        .mem_data       (mem_data),
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        .mem_valid      (mem_valid)
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);
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// +++--->>> One-Dimensional Fast Hartley Transform - 2nd Stage
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fht_1d_x8 #(N+3) u3_fht_1d_x8_2nd(
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        .rstn   (rstn),
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        .sclk   (sclk),
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        // input data
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        .x_valid        (mem_valid),
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        .x_data         (mem_data),
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        // output data
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        .fht_valid      (fht_2d_valid),
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        .fht_data       (fht_2d_data)
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);
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endmodule

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