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irezki |
/**********************************************************************
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* File : fht_1d_x8.v
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* Author: Ivan Rezki
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* email : irezki@gmail.com
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* Topic : RTL Core
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* 2-Dimensional Fast Hartley Transform
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*
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* Function: Fast Hartley Transform 1 Dimension for 8 Points
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* Decimation in Frequency Domain
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*
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* +-----------+ +-----------+ +-----------+
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* | Serial | | 1D FHT | | Parallel |
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* --->| to |--->| |--->| to |--->
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* | Parallel | | 8 Points | | Serial |
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* +-----------+ +-----------+ +-----------+
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*
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* RIGHT TO USE: This code example, or any portion thereof, may be
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* used and distributed without restriction, provided that this entire
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* comment block is included with the example.
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*
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* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
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* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
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* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
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* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
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* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
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* USE OF THIS CODE.
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**********************************************************************/
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2 |
irezki |
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module fht_1d_x8(
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rstn,
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sclk,
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// input data - x0,x1,x2,x3,x4,x5,x6,x7,x0,x1...
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x_valid,
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x_data,
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// 1D FHT output data - h0,h1,h2,h3,h4,h5,h6,h7,h0,h1...
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fht_valid,
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fht_data
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);
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parameter N = 8;
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input rstn;
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input sclk;
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input x_valid;
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input [N-1:0] x_data;
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output fht_valid;
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output [N+2:0] fht_data;
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// +++---------------------------------+++\\
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// +++ Data Preparation Step Start +++ \\
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// +++ - Aligning - +++ \\
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reg [N-1:0] x0,x1,x2,x3,x4,x5,x6,x7;
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always @(posedge sclk or negedge rstn)
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if (!rstn) begin
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x0 <= #1 0;
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x1 <= #1 0;
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x2 <= #1 0;
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x3 <= #1 0;
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x4 <= #1 0;
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x5 <= #1 0;
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x6 <= #1 0;
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x7 <= #1 0;
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end
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else if (x_valid) begin
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x0 <= #1 x_data;
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x1 <= #1 x0;
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x2 <= #1 x1;
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x3 <= #1 x2;
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x4 <= #1 x3;
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x5 <= #1 x4;
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x6 <= #1 x5;
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x7 <= #1 x6;
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end
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reg x_valid_1d;
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always @(posedge sclk or negedge rstn)
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if (!rstn) x_valid_1d <= #1 0;
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else x_valid_1d <= #1 x_valid;
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wire xi_ready;
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reg [2:0] cnt;
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always @(posedge sclk or negedge rstn)
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if (!rstn) cnt <= #1 0;
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else if (x_valid_1d) cnt <= #1 cnt + 1;
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assign xi_ready = (cnt == 7 && x_valid_1d) ? 1'b1 : 1'b0;
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// at the ready time aligned and reversed
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reg [N-1:0] x0_FF,x1_FF,x2_FF,x3_FF,x4_FF,x5_FF,x6_FF,x7_FF;
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always @(posedge sclk or negedge rstn)
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if (!rstn) begin
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x0_FF <= #1 0;
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x1_FF <= #1 0;
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x2_FF <= #1 0;
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x3_FF <= #1 0;
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x4_FF <= #1 0;
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x5_FF <= #1 0;
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x6_FF <= #1 0;
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x7_FF <= #1 0;
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end
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else if (xi_ready) begin
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x0_FF <= #1 x7;
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x1_FF <= #1 x6;
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x2_FF <= #1 x5;
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x3_FF <= #1 x4;
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x4_FF <= #1 x3;
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x5_FF <= #1 x2;
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x6_FF <= #1 x1;
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x7_FF <= #1 x0;
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end
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// +++ Data Preparation Step Finish +++ //
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// delay for ... clocks to provide timing requirements
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reg [13:0] xi_ready_d;
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always @(posedge sclk or negedge rstn)
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if (!rstn) xi_ready_d[13:0] <= #1 0;
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else xi_ready_d[13:0] <= #1 {xi_ready_d[12:0],xi_ready};
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// 1D Fast Hartley Transform - Decimation-in-Frequency Algorithm
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// Butterfly Stage N1
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// Data input [N-1:0] = N bits
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// On the output of the 1st bfly is [N:0] = N+1 bits
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// <<<--------- Butterfly Stage N1
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wire [N:0] stg1_sum1;
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wire [N:0] stg1_sum2;
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wire [N:0] stg1_sum3;
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wire [N:0] stg1_sum4;
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wire [N:0] stg1_sub1;
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wire [N:0] stg1_sub2;
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wire [N:0] stg1_sub3;
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wire [N:0] stg1_sub4;
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fht_bfly_noFF #(N) u11_fht_bfly ({x0_FF},{x4_FF},stg1_sum1,stg1_sub1);
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fht_bfly_noFF #(N) u12_fht_bfly ({x1_FF},{x5_FF},stg1_sum2,stg1_sub2);
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fht_bfly_noFF #(N) u13_fht_bfly ({x2_FF},{x6_FF},stg1_sum3,stg1_sub3);
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fht_bfly_noFF #(N) u14_fht_bfly ({x3_FF},{x7_FF},stg1_sum4,stg1_sub4);
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// <<<--------- Butterfly Stage N2
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wire [N+1:0] stg2_sum1;
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wire [N+1:0] stg2_sum2;
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wire [N+1:0] stg2_sum3;
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wire [N+1:0] stg2_sub1;
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wire [N+1:0] stg2_sub2;
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wire [N+1:0] stg2_sub3;
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fht_bfly #(N+1) u21_fht_bfly (rstn,sclk,xi_ready_d[1],stg1_sum1,stg1_sum3,stg2_sum1,stg2_sub1);
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fht_bfly #(N+1) u22_fht_bfly (rstn,sclk,xi_ready_d[1],stg1_sum2,stg1_sum4,stg2_sum2,stg2_sub2);
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fht_bfly #(N+1) u23_fht_bfly (rstn,sclk,xi_ready_d[1],stg1_sub1,stg1_sub3,stg2_sum3,stg2_sub3);
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// Multiplier on the 2nd Stage
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wire [N:0] mult_dat_1;
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wire [N:0] mult_dat_2;
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assign mult_dat_1 = stg1_sub2;
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assign mult_dat_2 = stg1_sub4;
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wire [N+1:0] mult_res1;
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wire [N+1:0] mult_res2;
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`ifdef USE_ASIC_MULT
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signed_mult_const_asic #(N+1) u_mult_1_fht (rstn,sclk,xi_ready_d[1],mult_dat_1,mult_res1);
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signed_mult_const_asic #(N+1) u_mult_2_fht (rstn,sclk,xi_ready_d[1],mult_dat_2,mult_res2);
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`elsif USE_FPGA_MULT
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signed_mult_const_fpga #(N+1) u_mult_1_fht (rstn,sclk,xi_ready_d[1],mult_dat_1,mult_res1);
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signed_mult_const_fpga #(N+1) u_mult_2_fht (rstn,sclk,xi_ready_d[1],mult_dat_2,mult_res2);
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`endif
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// <<<--------- Butterfly Stage N3
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wire [N+2:0] stg3_sum1;
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wire [N+2:0] stg3_sum2;
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wire [N+2:0] stg3_sum3;
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wire [N+2:0] stg3_sum4;
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wire [N+2:0] stg3_sub1;
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wire [N+2:0] stg3_sub2;
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wire [N+2:0] stg3_sub3;
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wire [N+2:0] stg3_sub4;
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fht_bfly #(N+2) u31_fht_bfly (rstn,sclk,xi_ready_d[3],stg2_sum1,stg2_sum2,stg3_sum1,stg3_sub1);
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fht_bfly #(N+2) u32_fht_bfly (rstn,sclk,xi_ready_d[3],stg2_sub1,stg2_sub2,stg3_sum2,stg3_sub2);
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fht_bfly #(N+2) u33_fht_bfly (rstn,sclk,xi_ready_d[3],stg2_sum3,mult_res1,stg3_sum3,stg3_sub3);
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fht_bfly #(N+2) u34_fht_bfly (rstn,sclk,xi_ready_d[3],stg2_sub3,mult_res2,stg3_sum4,stg3_sub4);
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// <<<--------- FHT Result
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reg [N+2:0] h0_FF,h1_FF,h2_FF,h3_FF,h4_FF,h5_FF,h6_FF,h7_FF;
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always @(posedge sclk or negedge rstn)
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if (!rstn) begin
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h0_FF <= #1 0;
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h4_FF <= #1 0;
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h2_FF <= #1 0;
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h6_FF <= #1 0;
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h1_FF <= #1 0;
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h5_FF <= #1 0;
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h3_FF <= #1 0;
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h7_FF <= #1 0;
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end
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else if (xi_ready_d[5]) begin
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h0_FF <= #1 stg3_sum1;
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h4_FF <= #1 stg3_sub1;
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h2_FF <= #1 stg3_sum2;
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h6_FF <= #1 stg3_sub2;
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h1_FF <= #1 stg3_sum3;
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h5_FF <= #1 stg3_sub3;
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h3_FF <= #1 stg3_sum4;
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h7_FF <= #1 stg3_sub4;
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end
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assign h0_valid = xi_ready_d[6];
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assign h1_valid = xi_ready_d[7];
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assign h2_valid = xi_ready_d[8];
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assign h3_valid = xi_ready_d[9];
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assign h4_valid = xi_ready_d[10];
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assign h5_valid = xi_ready_d[11];
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assign h6_valid = xi_ready_d[12];
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assign h7_valid = xi_ready_d[13];
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wire fht_valid_or;
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assign fht_valid_or = h0_valid |
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h1_valid |
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h2_valid |
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h3_valid |
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h4_valid |
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h5_valid |
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h6_valid |
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h7_valid ;
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wire [N+2:0] h_or_data;
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assign h_or_data =
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(h0_FF & {N+3{h0_valid}}) |
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(h1_FF & {N+3{h1_valid}}) |
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(h2_FF & {N+3{h2_valid}}) |
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(h3_FF & {N+3{h3_valid}}) |
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(h4_FF & {N+3{h4_valid}}) |
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(h5_FF & {N+3{h5_valid}}) |
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(h6_FF & {N+3{h6_valid}}) |
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(h7_FF & {N+3{h7_valid}}) ;
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reg [N+2:0] fht_data;
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reg fht_valid;
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always @(posedge sclk or negedge rstn)
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if (!rstn) fht_valid <= #1 0;
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else fht_valid <= #1 fht_valid_or;
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always @(posedge sclk or negedge rstn)
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if (!rstn) fht_data <= #1 0;
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else fht_data <= #1 h_or_data;
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endmodule
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