Subversion Repositories two_dimensional_fast_hartley_transform

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// The synthesis directives "translate_off/translate_on" specified below are

// supported by Xilinx, Mentor Graphics and Synplicity synthesis

// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file dpsram_128x16.v when simulating

// the core, dpsram_128x16. When compiling the wrapper file, be sure to

// reference the XilinxCoreLib Verilog simulation library. For detailed

// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module dpsram_128x16(

        addra,

        addrb,

        clka,

        clkb,

        dina,

        dinb,

        douta,

        doutb,

        ena,

        enb,

        wea,

        web);

input [6 : 0] addra;

input [6 : 0] addrb;

input clka;

input clkb;

input [15 : 0] dina;

input [15 : 0] dinb;

output [15 : 0] douta;

output [15 : 0] doutb;

input ena;

input enb;

input wea;

input web;

// synthesis translate_off

      BLKMEMDP_V6_3 #(

                .c_addra_width(7),

                .c_addrb_width(7),

                .c_default_data("0"),

                .c_depth_a(128),

                .c_depth_b(128),

                .c_enable_rlocs(0),

                .c_has_default_data(1),

                .c_has_dina(1),

                .c_has_dinb(1),

                .c_has_douta(1),

                .c_has_doutb(1),

                .c_has_ena(1),

                .c_has_enb(1),

                .c_has_limit_data_pitch(0),

                .c_has_nda(0),

                .c_has_ndb(0),

                .c_has_rdya(0),

                .c_has_rdyb(0),

                .c_has_rfda(0),

                .c_has_rfdb(0),

                .c_has_sinita(0),

                .c_has_sinitb(0),

                .c_has_wea(1),

                .c_has_web(1),

                .c_limit_data_pitch(18),

                .c_mem_init_file("mif_file_16_1"),

                .c_pipe_stages_a(0),

                .c_pipe_stages_b(0),

                .c_reg_inputsa(0),

                .c_reg_inputsb(0),

                .c_sim_collision_check("NONE"),

                .c_sinita_value("0"),

                .c_sinitb_value("0"),

                .c_width_a(16),

                .c_width_b(16),

                .c_write_modea(2),

                .c_write_modeb(2),

                .c_ybottom_addr("0"),

                .c_yclka_is_rising(1),

                .c_yclkb_is_rising(1),

                .c_yena_is_high(0),

                .c_yenb_is_high(0),

                .c_yhierarchy("hierarchy1"),

                .c_ymake_bmm(0),

                .c_yprimitive_type("32kx1"),

                .c_ysinita_is_high(1),

                .c_ysinitb_is_high(1),

                .c_ytop_addr("1024"),

                .c_yuse_single_primitive(0),

                .c_ywea_is_high(0),

                .c_yweb_is_high(0),

                .c_yydisable_warnings(1))

        inst (

                .ADDRA(addra),

                .ADDRB(addrb),

                .CLKA(clka),

                .CLKB(clkb),

                .DINA(dina),

                .DINB(dinb),

                .DOUTA(douta),

                .DOUTB(doutb),

                .ENA(ena),

                .ENB(enb),

                .WEA(wea),

                .WEB(web),

                .NDA(),

                .NDB(),

                .RFDA(),

                .RFDB(),

                .RDYA(),

                .RDYB(),

                .SINITA(),

                .SINITB());

// synthesis translate_on

endmodule