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[/] [mkjpeg/] [trunk/] [design/] [rle/] [RLE_TOP.VHD] - Blame information for rev 38

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-------------------------------------------------------------------------------
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-- File Name : RLE_TOP.vhd
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--
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-- Project   : JPEG_ENC
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--
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-- Module    : RLE_TOP
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--
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-- Content   : Run Length Encoder top level
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--
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-- Description :
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--
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-- Spec.     :
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--
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-- Author    : Michal Krepa
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--
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-------------------------------------------------------------------------------
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-- History :
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-- 20090301: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
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-------------------------------------------------------------------------------
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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library work;
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  use work.JPEG_PKG.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity RLE_TOP is
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  port
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  (
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        CLK                : in  std_logic;
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        RST                : in  std_logic;
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        -- CTRL
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        start_pb           : in  std_logic;
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        ready_pb           : out std_logic;
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        rle_sm_settings    : in T_SM_SETTINGS;
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        -- HUFFMAN
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        huf_buf_sel        : in  std_logic;
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        huf_rden           : in  std_logic;
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        huf_runlength      : out std_logic_vector(3 downto 0);
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        huf_size           : out std_logic_vector(3 downto 0);
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        huf_amplitude      : out std_logic_vector(11 downto 0);
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        huf_dval           : out std_logic;
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        huf_fifo_empty     : out std_logic;
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        -- Quantizer
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        qua_buf_sel        : out std_logic;
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        qua_rd_addr        : out std_logic_vector(5 downto 0);
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        qua_data           : in  std_logic_vector(11 downto 0);
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        -- HostIF
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        sof                : in  std_logic
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    );
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end entity RLE_TOP;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of RLE_TOP is
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  signal dbuf_data      : std_logic_vector(19 downto 0);
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  signal dbuf_q         : std_logic_vector(19 downto 0);
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  signal dbuf_we        : std_logic;
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  signal rle_runlength  : std_logic_vector(3 downto 0);
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  signal rle_size       : std_logic_vector(3 downto 0);
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  signal rle_amplitude  : std_logic_vector(11 downto 0);
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  signal rle_dovalid    : std_logic;
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  signal rle_di         : std_logic_vector(11 downto 0);
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  signal rle_divalid    : std_logic;
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  signal qua_buf_sel_s  : std_logic;
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  signal huf_dval_p0    : std_logic;
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  signal wr_cnt         : unsigned(5 downto 0);
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-------------------------------------------------------------------------------
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begin
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  huf_runlength <= dbuf_q(19 downto 16);
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  huf_size      <= dbuf_q(15 downto 12);
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  huf_amplitude <= dbuf_q(11 downto 0);
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  qua_buf_sel   <= qua_buf_sel_s;
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  -------------------------------------------------------------------
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  -- RLE Core
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  -------------------------------------------------------------------
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  U_rle : entity work.rle
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  generic map
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    (
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      RAMADDR_W  => 6,
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      RAMDATA_W  => 12
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    )
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  port map
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    (
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      rst        => RST,
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      clk        => CLK,
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      di         => rle_di,
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      start_pb   => start_pb,
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      sof        => sof,
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      rle_sm_settings => rle_sm_settings,
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      runlength  => rle_runlength,
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      size       => rle_size,
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      amplitude  => rle_amplitude,
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      dovalid    => rle_dovalid,
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      rd_addr    => qua_rd_addr
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    );
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  rle_di      <= qua_data;
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  -------------------------------------------------------------------
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  -- Double Fifo
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  -------------------------------------------------------------------
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  U_RleDoubleFifo : entity work.RleDoubleFifo
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  port map
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  (
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        CLK                => CLK,
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        RST                => RST,
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        -- RLE
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        data_in            => dbuf_data,
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        wren               => dbuf_we,
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        -- HUFFMAN
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        buf_sel            => huf_buf_sel,
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        rd_req             => huf_rden,
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        fifo_empty         => huf_fifo_empty,
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        data_out           => dbuf_q
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    );
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  dbuf_data  <= rle_runlength & rle_size & rle_amplitude;
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  dbuf_we    <= rle_dovalid;
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  -------------------------------------------------------------------
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  -- ready_pb
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  -------------------------------------------------------------------
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  p_ready_pb : process(CLK, RST)
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  begin
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    if RST = '1' then
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      ready_pb <= '0';
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      wr_cnt   <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      ready_pb <= '0';
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      if start_pb = '1' then
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        wr_cnt <= (others => '0');
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      end if;
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      -- detect EOB (0,0) - end of RLE block
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      if rle_dovalid = '1' then
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        -- ZERO EXTENSION
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        if unsigned(rle_runlength) = 15 and unsigned(rle_size) = 0 then
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          wr_cnt <= wr_cnt + 16;
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        else
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          wr_cnt <= wr_cnt + 1 + resize(unsigned(rle_runlength), wr_cnt'length);
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        end if;
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        -- EOB can only be on AC!
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        if dbuf_data = (dbuf_data'range => '0') and wr_cnt /= 0 then
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          ready_pb <= '1';
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        else
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          if wr_cnt + resize(unsigned(rle_runlength), wr_cnt'length) = 63 then
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            ready_pb <= '1';
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          end if;
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        end if;
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      end if;
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    end if;
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  end process;
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  -------------------------------------------------------------------
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  -- fdct_buf_sel
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  -------------------------------------------------------------------
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  p_buf_sel : process(CLK, RST)
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  begin
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    if RST = '1' then
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      qua_buf_sel_s   <= '0';
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    elsif CLK'event and CLK = '1' then
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      if start_pb = '1' then
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        qua_buf_sel_s <= not qua_buf_sel_s;
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      end if;
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    end if;
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  end process;
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  -------------------------------------------------------------------
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  -- output data valid
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  -------------------------------------------------------------------
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  p_dval : process(CLK, RST)
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  begin
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    if RST = '1' then
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      huf_dval_p0 <= '0';
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      --huf_dval    <= '0';
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    elsif CLK'event and CLK = '1' then
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      huf_dval_p0 <= huf_rden;
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      --huf_dval    <= huf_rden;
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    end if;
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  end process;
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  huf_dval    <= huf_rden;
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end architecture RTL;
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-------------------------------------------------------------------------------
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-- Architecture: end
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-------------------------------------------------------------------------------

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