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[/] [mkjpeg/] [trunk/] [design/] [JFIFGen/] [JFIFGen.vhd] - Blame information for rev 38

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1 25 mikel262
-------------------------------------------------------------------------------
2
-- File Name :  JFIFGen.vhd
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--
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-- Project   : JPEG_ENC
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--
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-- Module    : JFIFGen
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--
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-- Content   : JFIF Header Generator
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--
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-- Description :
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--
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-- Spec.     : 
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--
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-- Author    : Michal Krepa
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--
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-------------------------------------------------------------------------------
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-- History :
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-- 20090309: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
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-------------------------------------------------------------------------------
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.numeric_std.all;
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library work;
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  use work.JPEG_PKG.all;
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity JFIFGen is
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  port
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  (
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        CLK                : in  std_logic;
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        RST                : in  std_logic;
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        -- CTRL
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        start              : in  std_logic;
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        ready              : out std_logic;
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        eoi                : in  std_logic;
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        -- ByteStuffer
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        num_enc_bytes      : in  std_logic_vector(23 downto 0);
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        -- HOST IF
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        qwren              : in  std_logic;
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        qwaddr             : in  std_logic_vector(6 downto 0);
62 25 mikel262
        qwdata             : in  std_logic_vector(7 downto 0);
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        image_size_reg     : in  std_logic_vector(31 downto 0);
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        image_size_reg_wr  : in  std_logic;
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        -- OUT RAM
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        ram_byte           : out std_logic_vector(7 downto 0);
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        ram_wren           : out std_logic;
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        ram_wraddr         : out std_logic_vector(23 downto 0)
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    );
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end entity JFIFGen;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of JFIFGen is
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  constant C_SIZE_Y_H  : integer := 25;
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  constant C_SIZE_Y_L  : integer := 26;
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  constant C_SIZE_X_H  : integer := 27;
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  constant C_SIZE_X_L  : integer := 28;
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  constant C_EOI       : std_logic_vector(15 downto 0) := X"FFD9";
86 32 mikel262
  constant C_QLUM_BASE : integer := 44;
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  constant C_QCHR_BASE : integer := 44+69;
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  signal hr_data      : std_logic_vector(7 downto 0);
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  signal hr_waddr     : std_logic_vector(9 downto 0);
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  signal hr_raddr     : std_logic_vector(9 downto 0);
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  signal hr_we        : std_logic;
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  signal hr_q         : std_logic_vector(7 downto 0);
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  signal size_wr_cnt  : unsigned(2 downto 0);
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  signal size_wr      : std_logic;
97 36 mikel262
  signal rd_cnt       : unsigned(9 downto 0);
98 25 mikel262
  signal rd_en        : std_logic;
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  signal rd_en_d1     : std_logic;
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  signal rd_cnt_d1    : unsigned(rd_cnt'range);
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  signal rd_cnt_d2    : unsigned(rd_cnt'range);
102 25 mikel262
  signal eoi_cnt      : unsigned(1 downto 0);
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  signal eoi_wr       : std_logic;
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  signal eoi_wr_d1    : std_logic;
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  component HeaderRam is
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  port
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  (
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    d                 : in  STD_LOGIC_VECTOR(7 downto 0);
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    waddr             : in  STD_LOGIC_VECTOR(9 downto 0);
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    raddr             : in  STD_LOGIC_VECTOR(9 downto 0);
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    we                : in  STD_LOGIC;
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    clk               : in  STD_LOGIC;
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    q                 : out STD_LOGIC_VECTOR(7 downto 0)
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  );
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  end component;
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-------------------------------------------------------------------------------
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begin
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  -------------------------------------------------------------------
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  -- Header RAM
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  -------------------------------------------------------------------
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  U_Header_RAM : HeaderRam
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  port map
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  (
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        d           => hr_data,
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        waddr       => hr_waddr,
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        raddr       => hr_raddr,
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        we          => hr_we,
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        clk         => CLK,
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        q           => hr_q
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  );
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  hr_raddr <= std_logic_vector(rd_cnt);
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  -------------------------------------------------------------------
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  -- Host programming
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  -------------------------------------------------------------------
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  p_host_wr : process(CLK, RST)
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  begin
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    if RST = '1' then
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      size_wr_cnt <= (others => '0');
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      size_wr     <= '0';
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      hr_we       <= '0';
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      hr_data     <= (others => '0');
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      hr_waddr    <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      hr_we <= '0';
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      if image_size_reg_wr = '1' then
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        size_wr_cnt <= (others => '0');
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        size_wr     <= '1';
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      end if;
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      -- write image size
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      if size_wr = '1' then
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        if size_wr_cnt = 4 then
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          size_wr_cnt <= (others => '0');
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          size_wr     <= '0';
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        else
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          size_wr_cnt <= size_wr_cnt + 1;
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          hr_we <= '1';
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          case size_wr_cnt is
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            -- height H byte
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            when "000" =>
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              hr_data  <= image_size_reg(15 downto 8);
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              hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_H,hr_waddr'length));
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            -- height L byte
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            when "001" =>
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              hr_data <= image_size_reg(7 downto 0);
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              hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_L,hr_waddr'length));
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            -- width H byte
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            when "010" =>
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              hr_data <= image_size_reg(31 downto 24);
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              hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_H,hr_waddr'length));
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            -- width L byte
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            when "011" =>
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              hr_data <= image_size_reg(23 downto 16);
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              hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_L,hr_waddr'length));
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            when others =>
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              null;
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          end case;
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        end if;
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      -- write Quantization table
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      elsif qwren = '1' then
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        -- luminance table select
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        if qwaddr(6) = '0' then
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          hr_waddr <= std_logic_vector
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                        ( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
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                          to_unsigned(C_QLUM_BASE,hr_waddr'length));
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        else
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          -- chrominance table select
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          hr_waddr <= std_logic_vector
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                        ( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
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                          to_unsigned(C_QCHR_BASE,hr_waddr'length));
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        end if;
202 25 mikel262
        hr_we   <= '1';
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        hr_data <= qwdata;
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      end if;
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    end if;
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  end process;
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  -------------------------------------------------------------------
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  -- CTRL
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  -------------------------------------------------------------------
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  p_ctrl : process(CLK, RST)
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  begin
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    if RST = '1' then
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      ready      <= '0';
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      rd_en      <= '0';
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      rd_cnt     <= (others => '0');
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      rd_cnt_d1  <= (others => '0');
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      rd_cnt_d2  <= (others => '0');
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      rd_cnt_d1  <= (others => '0');
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      rd_en_d1   <= '0';
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      eoi_wr_d1  <= '0';
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      eoi_wr     <= '0';
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      eoi_cnt    <= (others => '0');
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      ram_wren   <= '0';
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      ram_byte   <= (others => '0');
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      ram_wraddr <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      ready     <= '0';
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      rd_cnt_d1 <= rd_cnt;
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      rd_cnt_d2 <= rd_cnt_d1;
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      rd_en_d1  <= rd_en;
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      eoi_wr_d1 <= eoi_wr;
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      -- defaults: encoded data write
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      ram_wren   <= rd_en_d1;
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      ram_wraddr <= std_logic_vector(resize(rd_cnt_d1,ram_wraddr'length));
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      ram_byte   <= hr_q;
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      -- start JFIF
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      if start = '1' and eoi = '0' then
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        rd_cnt <= (others => '0');
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        rd_en  <= '1';
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      elsif start = '1' and eoi = '1' then
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        eoi_wr  <= '1';
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        eoi_cnt <= (others => '0');
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      end if;
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      -- read JFIF Header
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      if rd_en = '1' then
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        if rd_cnt = C_HDR_SIZE-1 then
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          rd_en  <= '0';
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          ready  <= '1';
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        else
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          rd_cnt <= rd_cnt + 1;
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        end if;
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      end if;
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      -- EOI MARKER write
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      if eoi_wr = '1' then
261
        if eoi_cnt = 2 then
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          eoi_cnt  <= (others => '0');
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          eoi_wr   <= '0';
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          ready    <= '1';
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        else
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          eoi_cnt  <= eoi_cnt + 1;
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          ram_wren <= '1';
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          if eoi_cnt = 0 then
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            ram_byte   <= C_EOI(15 downto 8);
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            ram_wraddr <= num_enc_bytes;
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          elsif eoi_cnt = 1 then
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            ram_byte   <= C_EOI(7 downto 0);
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            ram_wraddr <= std_logic_vector(unsigned(num_enc_bytes) +
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                                           to_unsigned(1,ram_wraddr'length));
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          end if;
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        end if;
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      end if;
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    end if;
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  end process;
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281
end architecture RTL;
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-------------------------------------------------------------------------------
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-- Architecture: end
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-------------------------------------------------------------------------------

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