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UART 16550 core: Tracker : Does uart_int.v testcase run successfully? Monitor this item You will be notified via email when status of this item is changed or if somebody adds a comment. Your email   Does uart_int.v testcase run successfully? Type BUG Status OPENED I tried to run the supplied testcase, "uart_int.v", but it fails in ModelSim. The message in uart_interrupts_verbose.log is shown below: Time: 5734521200 (testbench.tx_fifo_status_changing) *E, Bit 5 of LSR register not '1'! I just wanted to verify that someone has successfully run the testcase before I spend any more time troubleshooting it. Regards, Dalton   Stats Nobody is monitoring this item Progress   Submited date 26-Nov-2006 Submited by dmarris@c...   Assigned date Assigned to   Closed date Closed by Comments by guenzel@e... on 06-Nov-2007 Well, the again. That simply got the simulation up and running, but it didn't fix the bug you reported. Sorry.   by guenzel@e... on 06-Nov-2007 I encountered an equal problem, which was related to the wb_sel_i decoding. The testcase (i.e. the wb_master) is always setting wb_sel_i to 4'hF which leads to masking off the lower two bits of the wb_addr (see uart_wb.v lines 293 and 301), because the case statements hit the default case. My solution was to change the lines 293 and 301 to: default: wb_adr_int_lsb = wb_adr_is[1:0]; If you dislike this 'hack', simply make the wb_master use the correct wb_sel_i values. best regards Robert   Add your comment Your email: Retype key: