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UART 16550 core: Tracker : Three bugs Monitor this item You will be notified via email when status of this item is changed or if somebody adds a comment. Your email   Three bugs Type BUG Status OPENED Codes at uart_regs.v 1. Changes tf_push to combinational logic 2. Changes msr[`UART_MS_CDCD:`UART_MS_CCTS] value from {dcd_c, ri_c, dsr_c, cts_c} to {~dcd_c, ~ri_c, ~dsr_c, ~cts_c} 3. Change modem outputs value from assign rts_n = mcr[`UART_MC_RTS]; assign dtr_n = mcr[`UART_MC_DTR]; To : assign rts_n = ~mcr[`UART_MC_RTS]; assign dtr_n = ~mcr[`UART_MC_DTR];   Stats 11 people are monitoring this item Progress   Submited date 25-Jan-2005 Submited by chenxj@w...   Assigned date Assigned to   Closed date Closed by Comments by designer@x... on 09-Oct-2007 I too have confirmed in hardware that 2 & 3 are definite bugs.   by victor_chan@t... on 18-Jul-2007 I agree with items 2 & 3. Rev. 0.6 of the specification call out the modem inputs and outputs to be inverted. I also tested my 16550 DUART in my ASCI and they are also inverted.   by el_tacano76@h... on 21-Dec-2005 The tf_push thing is quite a problem. This is because the fifo latches in the data the clock cycle after the write enable. If your write data remains valid for one more clock cycle then there is no problem, if the write data changes after the write enable (As in my case) you will get garbage written to the transmit fifo. As chenxj suggested changing the tf_push to combinational so it is valid one clock cycle earlier will fix the problem.   Add your comment Your email: Retype key: