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SPI controller core: Tracker : CTRL register bug Monitor this item You will be notified via email when status of this item is changed or if somebody adds a comment. Your email   CTRL register bug Type BUG Status OPENED Bit 0 of the CTRL register has a bug: when it is set by firmware, it can never ever be cleared again. This bit is part of the CHAR_LEN field which, according to the documentation, is R/W. But this is not the case. This means that the amount of data to transfer can never be changed to an even value if it ever gets set to an odd value. The problem is in spi_top.v. My suggested fix is to change this line: ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; to this: ctrl[7:0] <= #Tp wb_dat_i[7:0];   Stats 4 people are monitoring this item Progress   Submited date 19-Oct-2007 Submited by designer@x...   Assigned date Assigned to   Closed date Closed by Comments No comments yet.. Add your comment Your email: Retype key: