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In the Wishbone specification one can read that during a burst the wb_sel signal must be kept constant. One can obtain an error during such bursts if the dcqmem_ci_i signal wents high during the burst. The dcqmem_ci_i is in this case configured to correspond to the most significant bit in the address output from the cpu (dcpu_adr_cpu). DMMU and IMMU is disabled. The address from the cpu is erroneous in this case, and is produced in the LSU, where the LSU executes a LSUOP_NOP, and therefore signextends the ex_insn 16-bit immediate field. If bit ex_insn[15] is a one, one can possibly get an error, since then dcqmem_ci_i = dcpu_adr_cpu[31] = ex_insn[15]. The problem is that we observe a case where dcqmem_ci_i wents high during only one clockcycle during a cache refill burst, and therefore the wb_sel signal goes down for one clockcycle. Which in our case led to sampling old data, because of a too early ack signal.
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