LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Overview :: News :: Architecture :: OpenRISC 1200 :: VMware image :: NEW GNU Toolchain Port :: Architectural Simulator :: U-Boot :: Linux :: uClinux :: RTEMS :: ATS :: ORP :: ORPmon :: ORPsoc :: Survey :: Forum :: Silicon :: Downloads :: Tracker    

    OpenRISC 1000: Tracker : SMT/superscalar

    Monitor this item

    You will be notified via email when status of this item is changed or if somebody adds a comment.

    Your email

      SMT/superscalar

    Type IDEA
    Status OPENED
    Top
    Nice to se others having the same ideas (although alot earlier) about multithreading via register windows, but how about the idea of making it superscalar but not focusing on parellelism in threads but rather between several. This means having multiple IF frontends with a single issuing unit, thus having the apperance of an SMP system. I belive this is called Simultanious Multi Threading, or HyperThreading in Intel marketspeak.

    Now if only I had the time...
    /Anders

     
    Stats

    1 people are monitoring this item

    Progress
     
    Submited date 23-Nov-2004
    Submited by kaggen@s...
     
    Assigned date
    Assigned to
     
    Closed date
    Closed by

    Top

    Comments

    by luca-scalabrino@l... on 18-Nov-2005
    I agree. What about a speculative Tomasulo architecture? Luca
     

    Add your comment

    Your email:

    Retype key:
    Top

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.