LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Overview :: News :: Architecture :: OpenRISC 1200 :: VMware image :: NEW GNU Toolchain Port :: Architectural Simulator :: U-Boot :: Linux :: uClinux :: RTEMS :: ATS :: ORP :: ORPmon :: ORPsoc :: Survey :: Forum :: Silicon :: Downloads :: Tracker    

    OpenRISC 1000: Tracker : or1200_except.v

    Monitor this item

    You will be notified via email when status of this item is changed or if somebody adds a comment.

    Your email

      or1200_except.v

    Type BUG
    Status CLOSED
    Top
    Line 517

    Looks like two lines have been merged into one.

    After the:

    `ifdef OR1200_EXCEPT_TRAP

    there should be a line-break before

    13'b0_0000_0000_001x: begin

    I think?

     
    Stats

    Nobody is monitoring this item

    Progress
     
    Submited date 02-Oct-2004
    Submited by adrian@a...
     
    Assigned date
    Assigned to
     
    Closed date 23-Sep-2005
    Closed by Javier Castillo Villar

    Top

    Comments

    by Javier Castillo Villar on 23-Sep-2005
    That is not a bug. It works well without the line-break.
     

    Add your comment

    Your email:

    Retype key:
    Top

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.