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I am using the verilog I2C Controller (with WB interface removed) in my FPGA design. The I2C bus runs in 100kHz mode. The prescale register is set to 66, as the internal source clock is 33MHz. I would appreciate if you can address the below inquiries regarding "repeated start". []
When issuing a "repeated start", the required setup time is violated. The actual setup time is 2.01us instead of 4.7us. In a past correspondence from May 25, 2007, for avoiding timing violations you have proposed to generate "start" and then set read/write. However, it appears that "start" can not be generated on its own?! In other words, "start" must be set simultaneously either with "write" or "read", which results in the following: 1. Start+Write would always cause "repeated start" setup time violation. 2. Start+Read does not appear to be a valid I2C transaction and as such can not be used to generate "repeated start". As per I2C spec, "start" is always followed by a write operation (ex. slave address).
Moreover, the "Start+Read" transaction is also related to the "if branch" on line 261 in the Byte Controller FSM - state ST_START. Can you please explain under which circumstances the "if (read)" condition will be true, if any? I need this info for code coverage purposes. []
The following is a list of miscellaneous items that you may wish to address in a future release.
i2c_master_top.v - line 165: Misspelled "synopsys".
i2c_master_top.v - line 203: Use logical operator "!" instead of bitwise operator "~".
i2c_master_top.v - line 218: cr[0] register is 1-bit wide.
i2c_master_byte_ctrl.v - line 199: Misspelled "synopsys" Thank you in advance! Regards,
Viktor
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