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I2C controller core: Tracker : START doesn't satisfy Timing Requirements? Monitor this item You will be notified via email when status of this item is changed or if somebody adds a comment. Your email   START doesn't satisfy Timing Requirements? Type BUG Status CLOSED I just integrated the O.C. VHDL I2C Master module (with wishbone interface removed) and used the O.C. Verilog I2C Slave Module for testbenching. However, the slave module was catching timing violations for Start Setup Time, Start Hold Time, and Stop Setup Time. I'm using the I2C interface in 100kHz mode, where each period is 2us long (so 10us SCL), so the timing violations were due to several 2us transitions that didn't satisfy the 4.7us and 4us minimum times. My solution was to add three more Start states (e,f,g) and one Stop state to stretch the clock timing. It alters the duty cycle (more high time) for the SCL during these but as far as I can see in the standards a slower timing is acceptable.   Stats Nobody is monitoring this item Progress   Submited date 25-May-2007 Submited by jeremy.hannon@g...   Assigned date 25-May-2007 Assigned to Richard Herveille   Closed date 25-May-2007 Closed by Richard Herveille Comments by richard@h... on 25-May-2007 Not a bug. The core is designed to be as small as possible. If you need 100% timing either generate start and then set read/write or reduce the i2c clock frequency.   Add your comment Your email: Retype key: