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cpu65c02_tc - 65C02 Processor Soft Core with accurate timing: Tracker : New features - SWEET16 and two-port Monitor this item You will be notified via email when status of this item is changed or if somebody adds a comment. Your email   New features - SWEET16 and two-port Type IDEA Status OPENED Hello, Why not add SWEET16 into the 65C02? The design, by the Woz, is as clean as the 6502 itself and has a few slots for further expansion. Is true timing a must? If not I'd suggest making the zero page a on chip two port RAM, one port for zero page mode, the other for absolute mode. That way the zero page becomes the register file it should have been from the start.   Stats Nobody is monitoring this item Progress   Submited date 01-Aug-2008 Submited by alienthe@h...   Assigned date Assigned to   Closed date Closed by Comments by Jens Gutschmidt on 13-Aug-2008 Thanks for your input. I will think about the implementation of SWEET16. I'll give you a message in the next few days. -> True Timing - a must? Yes, this was an important point at the beginning of the design. There are many cores available on the web. But only very few of them are able to run like a real 6502/65C02 chip. Many of free cores have nor a RDY signal for working with DMA either a SYNC signal for single stepping. And the timing specifications of these cores are not the base for a direct 6502/65C02 replacement. Because of design considerations of the Disk ][ system working with a FPGA APPLE ][ the True Timing is a MUST. Thanks for your idea to implement a dual ported ram. I'll remember about this for future designs.   Add your comment Your email: Retype key: