LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Overview :: VHDL :: verilog :: News :: Downloads :: Tracker    

    CAN Protocol Controller: Tracker : the verilog code needs documentation

    Monitor this item

    You will be notified via email when status of this item is changed or if somebody adds a comment.

    Your email

      the verilog code needs documentation

    Type IDEA
    Status CLOSED
    Top
    Sir, even though the full verilog code is available for the controller, it is still difficult to understand the code without any documentation.

     
    Stats

    4 people are monitoring this item

    Progress
     
    Submited date 22-Nov-2005
    Submited by ravindra_bn@y...
     
    Assigned date
    Assigned to
     
    Closed date 23-Jan-2007
    Closed by Igor Mohor

    Top

    Comments

    by aitortxo@o... on 06-Nov-2008
    I have successfully simulated a transmitting frame. SJA1000 documentation helps a lot. Page 61 shows steps to write a register (see lower part) following those steps, some registers must be configured. 0) at the beginning, IP is in reset_mode. 1) set register 31 to define basicCAN or peliCAN 2) bus timing registers (6 and 7) if peliCAN 3) acceptance codes and masks (16 to 23) if peliCAN 4) leave reset_mode: register 0, with value 0 5) set register 16 to 28 with frame format (11/29 bit id) , remote_transfer/dataframe, data byte lenght with register(16), MSG id, and message data 6) now IP core is ready to send. Set register 1 with value 1 (TX_data) My problem is that i can't make it work in an implemented design. I can't even change the first register. I go to a state machine controlled by a pushbutton (this code is executed everytime button is pushed, incrementing int_cnt) case (int_cnt) 4'd1: ale_i = 1'b1; 4'd2: data_to_port = rd_i ? 8'bz : 8'd31; 4'd3: ale_i = 1'b0; 4'd4: cs_can_i = 1'b1; 4'd5: data_to_port = rd_i ? 8'bz : 8'b11000100; 4'd6: wr_i = 1'b1; 4'd7: wr_i = 1'b0; 4'd8: begin cs_can_i = 1'b0; NewStep = 1'b1; end endcase I have connected clkout_o to a pin to check freq with an oscilloscope, but it is changing 2*tclk, default value. So it is not changed actually. Please, can anyone help me set register's value? Thanks in advance Aitortxo.
     
    by chandravincent@g... on 15-Sep-2008
    Hai ,,,,,, could u provide me some assistance in the Implementation of the CAN controller, I require an internal block diagram for each block shown in the figure in this site. Could you help me somehow, Also i require some assistance regarding the Hardware implementation of the CAN controller Plz reply soon, Thanks in advance.plz send me the details to chandravincent@gmail.com
     
    by mdnaimaths@y... on 01-Apr-2007
    I do need the VHDL code for CAN controller . from where can i get it??? I need it urgently.... Thanks in advance.
     
    by mdnaimaths@y... on 01-Apr-2007
    I do need the VHDL code for CAN controller . from where can i get it??? I need it urgently.... Thanks in advance.
     
    by Igor Mohor on 23-Jan-2007
    For documentation take SJA1000 from Philips.
     
    by Igor Mohor on 23-Jan-2007
    SJA1000 from Philips will do the job.
     
    by Igor Mohor on 23-Jan-2007
    SJA1000 from Philips will do the job.
     
    by vj_v2@y... on 23-Jan-2007
    Hi, could u provide me some assistance in the Implementation of the CAN controller, I require an internal block diagram for each block shown in the figure in this site. Could you help me somehow, Also i require some assistance regarding the Hardware implementation of the CAN controller Plz reply soon, Thanks in advance. vj_v2@yahoo.com VJ
     

    Add your comment

    Your email:

    Retype key:
    Top

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.