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    Overview :: VHDL :: verilog :: News :: Downloads :: Tracker    

    CAN Protocol Controller: Tracker : Is the VHDL version not tested at all?

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      Is the VHDL version not tested at all?

    Type BUG
    Status CLOSED
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    Is the VHDL version tested at all? I tried to compile the code with modelsim and I got allot of syntax errors.


    ANSWER:
    As far as I know the VHDL code was rewritten in VHDL (and is not up-to-date). I know nothing about testing it. Ask the author of the VHDL part.
    And please use the cores@o... mailing list for questions. This section is reserved for "BUG reporting".
    Regards,
    Igor Mohor

     
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    Submited date 08-Apr-2004
    Submited by patrik.green@j...
     
    Assigned date
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    Closed date 08-Apr-2004
    Closed by Igor Mohor

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    Comments

    by shehryar.shaheen@u... on 08-Apr-2004
    The CAN VHDL core will complie in ModelSim with the following commad line vcom -93 -explicit *.vhd The core is not up-to-date according to the Verilog core and has not been tested in hardware.
     

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