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Research Engineer.
| Type |
IDEA |
| Status |
CLOSED |
Although the Verilog source looks to be well structured, it is still very difficult to follow.
The SJA1000 documentation is good to describe the operation of the controller but I feel some additional code specific documentation is needed in order for this CAN Controller to be useful to the designer.
Even some documentation on the interfacing and synthesis would be helpful.
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