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Break state persists after condition cleared
| Type |
BUG |
| Status |
CLOSED |
Bit 4 of the Line Status Register is meant to indicate whether a break state has occurred. According to the datasheet for the PC16550D, this bit should be cleared when the LSR is read. However, if the RBR register is read after reading the LSR register, and no additional data has yet come in, the Break Interrupt reappears.
This could be attributed to line 840 of gh_uart_16550.vhd which will set the "Break Interrupt" bit if RF_DO(10) is high. Since this line never checks if the FIFO is empty (and, therefore, if the 11-bit word in the RX FIFO is valid), it will always keep iBreak_ITR at a logic one if the last byte in the FIFO is the break byte. (Note the last byte in the FIFO never really "goes away" until another byte replaces it.) When RBR is read, iBreak_ITR is pulled low briefly due to the RF_RD signal. This allows component U32c to detect another rising edge and reassert the Break Interrupt bit.
It seems to me the code should not reassert the Break Interrupt bit if the break byte in question has already been read out.
I would recommend replacing line 840 with code similar to the following:
iBreak_ITR <= RF_DO(10) and (not RF_RD) and (not RF_EMPTY);I'm open to other interpretations of the proper functionality, as I'm not fully confident in how I'm reading the PC16550D spec, but it seems like this is unexpected behavior.
Regards,
~Nathan Z.
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