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a VHDL 16550 UART core: Tracker : Clearing Receiver Line Status Interrupt Monitor this item You will be notified via email when status of this item is changed or if somebody adds a comment. Your email   Clearing Receiver Line Status Interrupt Type BUG Status CLOSED When using the Receiver Line Status Interrupt (IER(2) = 1) I observe the following behaviour: * A character with parity, framing or break error was received and the LS interrupt is set. * When now the LSR is read, the LS interrupt is not cleared how it is described in the IIR. * But when the top character from the Rx FIFO is read then the LS interrupt is cleared immediately. What I expect is that the LS interrupt can be cleared by reading the LSR any time, independently of the top charater in the Rx FIFO. Matthias Klemm   Stats 1 people are monitoring this item Progress   Submited date 11-Oct-2007 Submited by mklemm@d...   Assigned date 13-Oct-2007 Assigned to Howard A. LeFevre   Closed date 13-Oct-2007 Closed by Howard A. LeFevre Comments by mklemm@d... on 12-Oct-2007 It seems that I found a solution. I changed the following code in gh_uart_16550.vhd: OLD: ==== Parity_ER <= RF_DO(8); FRAME_ER <= RF_DO(9); Break_ITR <= RF_DO(10); ITR3 <= '0' when (IER(2) = '0') else '1' when (LSR(1) = '1') else '1' when (RF_DO(10 downto 8) > "000") else '0'; NEW: ==== parity_er_edge_det : gh_edge_det PORT MAP ( clk => clk, rst => rst, d => RF_DO(8), re => Parity_ER); FRAME_er_edge_det : gh_edge_det PORT MAP ( clk => clk, rst => rst, d => RF_DO(9), re => FRAME_ER); Break_ITR_edge_det : gh_edge_det PORT MAP ( clk => clk, rst => rst, d => RF_DO(10), re => Break_ITR); ITR3 <= '0' when (IER(2) = '0') else '1' when (LSR(1) = '1') else '1' when (LSR(4 downto 2) > "000") else '0'; In my test it worked fine.   Add your comment Your email: Retype key: