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a VHDL 16550 UART core: Tracker : Clock configuration is wrong Monitor this item You will be notified via email when status of this item is changed or if somebody adds a comment. Your email   Clock configuration is wrong Type BUG Status CLOSED The comments about the clock configuration are correct. The baud rate generator creates a clock enable which is used by the Transmitter and Receiver modules – they operate at the same rate as B_CLK. As long as the user wants to use the Baud rate generator to set the baud rate, there is no problem. If some one wants to by-pass the Baud rate generator, it should be easy modify the source code.   Stats Nobody is monitoring this item Progress   Submited date 12-Oct-2006 Submited by dmarris@c...   Assigned date 12-Oct-2006 Assigned to Howard A. LeFevre   Closed date 12-Oct-2006 Closed by Howard A. LeFevre Comments No comments yet.. Add your comment Your email: Retype key: