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UART 16550 core: Tracker Show All OPENED and CLOSED OPENED CLOSED DELETED Feature requests Date Title Status Assigned to Submited by # 04-Aug-2006 about rs OPENED np02030418@t... 0 04-Aug-2005 VHDL Implementation OPENED jaganj@m... 0 Post request for new feature Bugs Date Title Status Assigned to Submited by # 19-Jul-2007 TERI in Modem Status Register Not To Specification OPENED victor_chan@t... 0 26-Nov-2006 Does uart_int.v testcase run successfully? OPENED dmarris@c... 2 19-May-2006 Need to fix commenting-out style in rtl/verilog/uart_defines.v OPENED jcollins@l... 3 15-May-2006 Need to fix commenting-out style in rtl/verilog/uart_defines.v OPENED jcollins@l... 0 14-Oct-2005 student OPENED paul_cooke_98@y... 1 06-Jul-2005 Typo in documentation OPENED spam@a... 0 25-Jan-2005 Three bugs OPENED chenxj@w... 3 21-Dec-2004 wishbone SEL_I problem CLOSED luke.darnell@g... 0 Report bug Ideas No bugs found Post idea Reminders No bugs found Add reminder (only maintainer of this project can do this)