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a VHDL 16550 UART core: Tracker Show All OPENED and CLOSED OPENED CLOSED DELETED Feature requests No feature request found Post request for new feature Bugs Date Title Status Assigned to Submited by # 21-Jul-2008 Break state persists after condition cleared CLOSED Howard A. LeFevre nzeitler@o... 1 18-Jun-2008 Transmit Interrupt doesn't fire during a Single Byte Send CLOSED Howard A. LeFevre auchter@u... 3 11-Oct-2007 Clearing Receiver Line Status Interrupt CLOSED Howard A. LeFevre mklemm@d... 1 10-Oct-2007 Enabling THRE Interrupt CLOSED Howard A. LeFevre djj08230@g... 1 06-Aug-2007 Fifos' reset doesn't work CLOSED Howard A. LeFevre astenu@w... 0 06-Aug-2007 Fifos' reset doesn't work CLOSED Howard A. LeFevre astenu@w... 0 02-Aug-2007 Timeout interrupt CLOSED Howard A. LeFevre astenu@w... 1 12-Oct-2006 Clock configuration is wrong CLOSED Howard A. LeFevre dmarris@c... 0 Report bug Ideas No bugs found Post idea Reminders No bugs found Add reminder (only maintainer of this project can do this)