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RISC_Core_I: Overview
| Details Name: risc_core_i
Created: 29-Dec-2001 14:54:16
Updated: 17-Jan-2002 13:15:49
CVS: no files in cvs Other project properties Category :: Microprocessor
Development status :: Planning
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motivation
This project is my diploma paper i have written to gratuate at the University of Applied Sciences St.Gallen (Switzerland).
Description
This is a 4 stage 16-Bit RISC processor system on chip designed for a Xilinx Virtex FPGA. RAM and ROM both are blockRAM based.
Additionally, it is equiped with a parallel multiplier, a 8-Bit input and a 8-Bit output port.
This core wasn't designed for commercial but for educational use. RAM, ROM and the ports are designed with the schematic editor from Xilinx ISE. RAM and ROM are dual ported for an additional access over a pci bridge. The CPU is programmed in VHDL.
Remark
The papers are written in german.
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