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Serial Uart: Overview Details Name: miniuart2 Created: 20-Jan-2002 13:35:37 Updated: 21-Jan-2003 12:00:42 CVS: browse Other project properties Category :: Communication controller Standard :: Wishbone compliant core Development status :: Mature Project maintainers Carton Statistics view Description Design in VHDL: This UART is able to Transmit/Receive bytes in the configuration: 1 start bit - no parity - 1 stop bit. It can be commanded by a microcontroller, or by other IP core. It is not suited to interface a modem as there is no control handshaking (CTS/RTS). It does'nt contain FIFO for emit/receive. Features • WISHBONE interface in 8-bit data bus • Two clock: one for wishbone interface, one for RS232 bitstream generation • Baudrate divisor from 1 to 65536 (generic parameter set at integration time) Synthesis results Xilinx: • Spartan: XCS10-TQ144-4: 71 flip-flop • Spartan-II: XC2S15-CS144-6: 153BELs@107MHz Status Operational