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DES/Triple DES IP Cores: Overview
Description
Simple DES/Triple-DES core.
Motivation
- A simple DES core
- Fast and Small Version
- Open Source
Compatibility
I believe that the core complies to NIST-800-17. However, there has been no formal third party verification. The official NIST specification can be downloaded here: 800-17.pdf. For the Triple DES, the NIST reference is located here: FIP46-3.
Performance
Triple DES IP Core
============== 1) Area Optimized (CBC Mode)
This is a sequential implementation and needs 48 cycles to complete a full encryption/decryption cycle.
- 0.18u UMC ASIC process: 5.5K gates, > 160 Mhz
- Spartan IIe 100-6 : 1450 LUTs (about 60%), 88MHz
2) Performance Optimized (EBC Mode)
This is a pipelined implementation that has a 48 cycle pipeline (plus 1 input and 1 output register). It can perform a complete encryption/decryption every cycle.
- 0.18u UMC ASIC process: 55K Gates, 300MHz (19.2 Gbits/sec)
- Virtex-II-1500-6: 79% utilization, 166Mhz (10.6 Gbits/sec)
(Single) DES IP Core
==================1) Area Optimized (CBC Mode)
This is a sequential implementation and needs 16 cycles to complete a full encryption/decryption cycle.
- 0.18u UMC ASIC process: >155Mhz 3K Gates
- Xilinx Spartan IIe-50: >100 MHz 1339 LUTs (87% device utilization)
- Altera APEX 20KE-1: 1106 lcells >27MHz
- Altera FLEX 10K50E-1: 1283 lcells >43MHz
2) Performance Optimized (EBC Mode)
This is a pipelined implementation that has a 16 cycle pipeline (plus 1 input and 1 output register). It can perform a complete encryption/decryption every cycle.
- 0.18u UMC ASIC process: >290Mhz 28K Gates
- Xilinx Spartan IIe-200: 140 MHz 4448 LUTs (94% device utilization)
- Altera APEX 20KE-1: 6688 lcells >53MHz
- Altera FLEX 10K130E-1: 6485 lcells >76 Mhz
Implementing the core
Nothing special about implementing the core.
Status
- Thanks to Sakamoto Yasuhiro for providing a key select unit that is 50% smaller than the original ! It has been updated in the area optimized version, but might also be applicable for other versions.
- Added a triple DES version
- Added many more test vectors to the single DES version
- Added Encrypt/Decrypt input (Thanks to Mark Cynar for providing the code)
- Changed Directory Structure
- Improved test benches
Change log
- 10/7/2004 RU - Updated key select unit in the are optimized version
- 31/10/2002 RU - Added Triple DES versions
- 28/9/2002 RU - Added Xilinx Spartan 2e synthesis results
- 10/6/2001 RU - Updated Directory Structure, added encrypt/decrypt, improved test bench
- 9/14/2000 RU - Initial release
This IP Core is provided by:
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